Abstract: Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.

Abstract: An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column.

Abstract: A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die is an integrated passive die (IPD) without a silicon substrate layer. A protective layer is disposed over the IPD, wherein the protective layer has a thermal conductivity between 2 watts per meter Kelvin (W/mK) and 6600 W/mK and an electrical resistivity of greater than 106 Ohm-cm.

Abstract: A wiring substrate includes a first wiring layer, an insulative resin first insulation layer covering the first wiring layer, and a second wiring layer located on an upper surface of the first insulation layer. A via wiring layer, which extends through the first insulation layer to connect the first and second wiring layers, includes an upper end surface connected to the second wiring layer and flush with the upper surface of the first insulation layer. The second wiring layer has a higher wiring density than the first wiring layer. The first insulation layer includes a first resin layer and a second resin layer located on an upper surface of the first resin layer and having a lower filler content rate than the first resin layer. The upper surface of the first resin layer is a curved surface upwardly curved toward the upper end surface of the via wiring layer.

Abstract: A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate pattern having a second height, an insulating pattern on the substrate covering the first and second gate patterns, the insulating pattern including a trench exposing the substrate between the first and second gate patterns, a spacer contacting at least a portion of a sidewall of the insulating pattern within the trench, the spacer spaced apart from the first and second gate patterns and having a third height larger than the first and second heights, and a contact structure filling the trench.

Abstract: A device substrate and a fabricating method thereof are provided. The device substrate includes a substrate and a patterned light-shielding layer. The patterned light-shielding layer having a plurality of pixel openings and a plurality of first exposure openings is disposed on the substrate, and an area and/or shape of one of the first exposure openings is different from an area and/or shape of one of the pixel openings.

Abstract: An embodiment of a silicon carbide semiconductor device includes one or more inner cells each having a MOSFET and one or more outer peripheral cells that does not have a MOSFET structure, and the area (surface area) of the p+ contact region of each of the outermost peripheral cells is less than the surface area of an p+ contact region of each of the inner cells, for example, so that a unit total resistance of p+ contact regions of the outermost peripheral cells, as measured in a depth direction of the semiconductor substrate with respect to a unit area in a surface of the semiconductor substrate, is greater than a unit total resistance of the p+ contact regions of the inner cells, as measured in the depth direction of the semiconductor substrate with respect to the unit area in the surface of the semiconductor substrate.

Abstract: A lead frame includes a first lead frame including a first lead; a second lead frame including a second lead, the second lead frame being stacked on the first lead frame so that a space is formed between the first lead frame and the second lead frame, and the second lead being bonded to the first lead; and a resin portion provided in the space formed between the first lead frame and the second lead frame, wherein each of the first lead and the second lead includes an embedded portion embedded in the resin portion, and a protruding portion protruded from the resin portion, and wherein the embedded portion of the first lead and the embedded portion of the second lead are bonded in the resin portion.

Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.

Abstract: A lightweight flexible light-emitting device that is less likely to be broken is provided. The light-emitting device includes a first flexible substrate, a second flexible substrate, an element layer, a first bonding layer, and a second bonding layer. The element layer includes a light-emitting element. The element layer is provided between the first flexible substrate and the second flexible substrate. The first bonding layer is provided between the first flexible substrate and the element layer. The second bonding layer is provided between the second flexible substrate and the element layer. The first and second bonding layers are in contact with each other on the outer side of an end portion of the element layer. The first and second flexible substrates are in contact with each other on the outer side of the end portions of the element layer, the first bonding layer, and the second bonding layer.

Abstract: Techniques are provided for forming thin film transistors having a polycrystalline silicon active layer formed by metal-induced crystallization (MIC) of amorphous silicon in an oxidizing atmosphere. In an aspect, a transistor device, is provided that includes a source region and a drain region formed on a substrate, and an active channel region formed on the substrate and electrically connecting the source region and the drain region. The active channel region is formed with a polycrystalline silicon layer having resulted from annealing an amorphous silicon layer formed on the substrate and having a metal layer formed thereon, wherein the annealing of the amorphous silicon layer was at least partially performed in an oxidizing ambience, thereby resulting in crystallization of the amorphous silicon layer to form the polycrystalline silicon layer.

Abstract: A conducting package structure includes a substrate and a conducting material. The conducting material is formed to a first patterned structure. The first patterned structure has a first surface which is connected to the substrate and a patterned second surface opposite to the first surface.

Abstract: The present application discloses a light-emitting element comprising a semiconductor light-emitting stack emitting a first light which has a first color coordinate, a first wavelength conversion material on the semiconductor light-emitting stack converting the first light to emit a second light, and a second wavelength conversion material on the first wavelength conversion material converting the second light to emit a third light. The first light and the second light are mixed to be a fourth light having a second color coordinate. The third light and the fourth light are mixed to be a fifth light having a third color coordinate, and the second color coordinate locates at the top right of the first color coordinate and the third color coordinate locates at the top right of the second color coordinate.

Abstract: A liquid crystal display includes a first substrate, a gate line and a data line disposed on the first substrate, a first insulating layer disposed on the gate line and the data line, a first electrode disposed on the first insulating layer and having a flat form in a planar shape, a second insulating layer disposed on the first electrode, and a second electrode disposed on the second insulating layer and including a plurality of branch electrodes, where a width of a branch electrode of the plurality of branch electrodes is equal to or less than about 2 micrometers.

Abstract: A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

Abstract: A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads.

Abstract: A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.

Abstract: The present invention provides an array substrate, which includes a plurality of pixel units, each pixel unit includes a thin film transistor, a pixel electrode, a common electrode and a passivation layer, the thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode, the drain electrode and the pixel electrode are connected, the passivation layer is disposed on the active layer, the source electrode, the drain electrode and the pixel electrode, the common electrode is disposed above the pixel electrode with the passivation layer therebetween, a test electrode is disposed on the active layer and under the passivation layer, the test electrode is electrically insulated from the gate electrode, the source electrode and the drain electrode. Correspondingly, a method for fabricating and a method for testing the array substrate, and a display device including the array substrate are provided.

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a first transistor region, a second transistor region and a silicon dioxide layer on the first transistor region and the second transistor region. A layer of a high-k dielectric material is deposited on the silicon dioxide layer. A layer of a first metal is formed over the second transistor region. The layer of first metal does not cover the first transistor region. After the formation of the layer of the first metal, a layer of a second metal is deposited over the first transistor region and the second transistor region. A first annealing process is performed. The first annealing process initiates a scavenging reaction between the second metal and silicon dioxide from a portion of the silicon dioxide layer on the first transistor region. After the annealing process, a ferroelectric transistor dielectric is formed over the first transistor region.

Abstract: Provided is a Schottky diode. The Schottky diode includes: a substrate; a core on the substrate; a metallic layer on the core; and a shell surrounding the core between the metallic layer and the substrate and adjusting a Fermi energy level of the core to form a Schottky junction between the core and the metallic layer.