Abstract: In an embodiment, an antenna unit for an antenna array allows shifting the phase of a radiated or received signal without the need for a phase shifter, and includes an antenna element, switching devices, and signal couplers. The antenna element includes at least one section and signal ports each electrically isolated from each other and from each of the at least one section. The switching devices are each configured to couple a respective one of the signal ports to one of the at least one section in response to a respective control signal, and the signal couplers are each configured to couple a respective one of the signal ports to a respective location of a respective transmission medium.

Abstract: An electronic device may include a rear housing wall, antenna resonating element, coil, sensor board, and antenna grounding ring structures. The coil may receive wireless charging signals through the grounding ring structures and the rear housing wall. The grounding ring structures may include concentric ring-shaped traces. The ring-shaped traces may be separated by at least one gap. The ring-shaped traces and the gaps may configure the grounding ring structures to short antenna currents at relatively high frequencies from the antenna resonating element to a ground trace on the sensor board while blocking currents at relatively low frequencies. This may allow the ground trace to form part of an antenna without substantially impairing wireless charging efficiency of the coil.

Abstract: The contemplated system allows users to engage in a recording activity with studio quality light. Because the system is portable and easily deployable, the system can be carried to and quickly set up by the user in any location where the recording will occur. The system includes a lighting instrument that can be installed on the display with the web camera exposed. The lighting instrument includes a light source configuration that can reduce lens flare. The system allows for operation as a dock station when not deployed. The contemplated method allows users to operate the system. The method helps the user achieve the optimal light intensity and angle for the recording area with reduced time and efforts. The method may consider distance, ambient light, location of the subject and other factors in its determination. The method allows users to further adjust the intensity and angle if necessary.

Abstract: A load control system includes a controller that modifies an alternating current (AC) signal at a controller input to provide, on a cycle-by-cycle basis, an encoded AC signal that exhibits a unique AC signature at a controller output. The unique AC signature is associated with a particular user-selectable load characteristic. The load control system also includes a load circuit that receives the encoded AC signal. The load circuit includes a decoder that decodes the encoded AC signal to determine the unique AC signature of the encoded AC signal. In response to determining the unique AC signature of the encoded AC signal, the load circuit changes a load characteristic of the load circuit to exhibit the particular user-selectable load characteristic associated with the unique AC signature.

Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.

Abstract: Different functional elements are all located on a same integrated circuit wherein at least one of the functional elements comprises a micro-controller. Configuration registers or configuration memory in the integrated circuit store configuration values loaded by the micro-controller. Connectors are configured to connect the integrated circuit to external signals. A system level interconnect also located in the integrated circuit programmably connects together the different functional elements and different connectors according to the configuration values loaded into the configuration registers.

Abstract: An on die termination controls a terminal resistance value in accordance with a test signal. The one die termination device comprises an on die termination control unit and an on die termination resistor unit and can change the terminal resistance value in accordance with the test signal, so that the terminal resistance can be easily analyzed. The one die termination control unit comprises a resistance control enable signal generating unit and a resistance control signal generating unit and generates at least one resistance increment signal and at least one resistance decrement signal. The on die termination resistor unit comprises a resistor and a plurality of switch units that are connected in parallel and is driven by a driving signal and uses the resistance increment signal and resistance decrement signal to control the on die termination resistance value.

Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that includes several configurable circuits that are conceptually in tiles. The IC also includes a first data network for passing data between the configurable circuits. The IC further includes a second packet-switch network for receiving packets of data from the outside of the configurable IC and switchably routing each packet to at least one destination tile. In some embodiments, the second packet-switch network supplies data from the tiles that the configurable circuits output in response to data packets received from outside of the configurable IC. Also, in some embodiments a particular packet that is for a particular resource in a particular tile includes a first address that identifies the particular configurable tile from the plurality of configurable tiles, and then a second address that identifies the particular resource within the particular configurable tile.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits for configurably performing computations. The configurable IC also includes several configurable routing circuits for configurable routing signals to and from the logic circuits. In some embodiments, at least a set of the routing circuits are routing/storage circuits. Each routing/storage circuit has an output and a storage section at the output for controllably storing a signal that the routing/storage circuit produces at the output.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: The impedance of a driver driving a load on the other end of a transmission line is dynamically changed to improve slew rate and glitch termination. The driver is controlled to have a low impedance during an initial part of an edge transition, giving the strong drive needed at that time. At a first predetermined position in the edge transition, approximately equal to the flight time, the driver impedance is raised to a value approximately equal to the transmission line impedance to effectively terminate any reflected signals.

Abstract: Circuit arrangement, and a method of its operation, for substantially reducing the running times in clocked logic circuits by eliminating conventional storage registers and by controlling the signal flow by parallel connection to the output of a gate or other signal transmitting circuit component of an additional current source which may be changed by the clock pulse.

Abstract: The differential MOS current-mode logic structure of the present invention is comprised of a differential MOS transistor pair and a complementary MOS (CMOS) transistor for each of the transistors comprising the differential MOS pair. The gates of the CMOS transistors are coupled to the gates of the differential MOS pair. Since the gates of the differential MOS pair receive a differential signal from the inputs, the voltage between the gate and the source, Vgs, for each of the transistors comprising the MOS differential pair is not fixed. As a result, the gain of the CMOS current-mode logic structure of the present invention is high. In addition, since the gates of the CMOS transistors are coupled to the gates of the differential MOS pair, the current for the CMOS transistors is increased when charging the node capacitance and is decreased when discharging the node capacitance.