Patents Examined by Ahn Tran
  • Patent number: 10193711
    Abstract: Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips. Each of the plurality of chips further includes a terminal coupled to the resistor and a calibration circuit. The calibration circuit determines whether the resistor is available based, at least in part, on timing information that is unique to a corresponding chip of the plurality of chip. The timing information of each chip of the plurality of chips has a fixed duration of time common to the plurality of chips.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: January 29, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Christopher G. Wieduwilt, Jason Johnson
  • Patent number: 10117309
    Abstract: An apparatus comprising a battery, a power adapter and a base. The battery may be configured to provide a power source. The power adapter may be configured to (a) receive AC power, (b) provide the AC power to a device and (c) convert the AC power to DC power. The power adapter may be implemented in a socket adapter for the device. The base may comprise a circuit and a camera sensor. The circuit may be configured to provide a connection to (i) the camera sensor, (ii) the battery and (iii) the DC power. Video data captured by the camera sensor may be sent via wireless communication. The circuit may be configured to generate control signals for activation of (i) the device and (ii) components of the circuit. The power source may provide power to the circuit and the camera sensor.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: October 30, 2018
    Assignee: KUNA SYSTEMS CORPORATION
    Inventors: Sai-Wai Fu, Haomiao Huang
  • Patent number: 9374864
    Abstract: A controller circuit is configured to adjust the number of light-emitting diodes that a current flows from a rectifier circuit through so that: the number of light-emitting diodes, which are lit, of the plurality of light-emitting diodes increases according to a value of a pulsating voltage during a time period that the value of the pulsating voltage increases; and the number of light-emitting diodes, which are lit, of the plurality of light-emitting diodes decreases according to the value of the pulsating voltage during a time period that the value of the pulsating voltage decreases. Light-emitting diodes, which start to emit light by a higher voltage value, of the plurality of light-emitting diodes are disposed at a position nearer to an outside of a mounting region of a substrate than light-emitting diodes, which start to emit light by a lower voltage value, of the plurality of light-emitting diodes.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 21, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Takeshi Kamoi, Akinori Hiramatu, Hiroshi Kido, Katsushi Seki, Shigeru Ido, Daisuke Yamahara, Daisuke Ueda
  • Patent number: 9362918
    Abstract: The invention relates to a programmable interconnection device, comprising: first rows of functional blocks, each functional block having inputs and outputs; second rows of programmable interconnection cells; horizontal connections, each connecting a programmable interconnection cell of the second row with only one other cell of that row; and connection bundles comprising transverse connections connecting a given programmable interconnection cell with functional blocks of the neighboring first row; the cells being suitable together for interconnecting the inputs and the outputs of each functional block of each first row with the outputs and the inputs of all of the other functional blocks of the same row.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: June 7, 2016
    Assignee: NANOXPLORE
    Inventor: Olivier Lepape
  • Patent number: 9300294
    Abstract: Various systems and methods are provided for integrated circuit clocking. In one embodiment, an integrated circuit system includes a plurality of combinational logic groups, each combinational logic group having a propagation time; and means for delaying a synchronizing clock signal supplied to at least one of the plurality of combinational logic groups based upon a period of the synchronizing clock signal and the propagation time of the at least one combinational logic group. In another embodiment, a method includes delaying a clock signal to produce a delayed clock signal and communicating the clock signal and the delayed clock signal to separate groups of the combinational logic circuit during a clock cycle that results in a reduction in power consumption by the combinational logic circuit.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: March 29, 2016
    Assignee: East-West Innovation Corporation
    Inventors: Deanne Tran Vo, Thomas Jeffrey Bingel
  • Patent number: 9247603
    Abstract: A light emitting diode lighting assembly that receives an electrical excitation signal that is varied from a dimming device. Driving circuitry receives the varying input and has first and second paths that each have a plurality of light emitting diodes. Each plurality of light emitting diodes has a threshold voltage with the threshold voltage of the first plurality of diodes being less than the threshold voltage of the second plurality of lighting emitting diodes. The current within the first path is controlled by a current limiting device that is controlled by a resistor that receives input from the second path to gradually turn off the first plurality of light emitting diodes as the second plurality of lighting emitting diodes increase in intensity. A shunt voltage regulator within the circuit having a threshold voltage that is above threshold voltages of components in the assembly to minimize voltage increases in the assembly.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: January 26, 2016
    Assignee: Once Innovations, Inc.
    Inventors: Zdenko Grajcar, Leif Erickson
  • Patent number: 9060401
    Abstract: Apparatus and method are disclosed for providing AC line power to lighting devices such as light emitting diodes (“LEDs”). A representative apparatus comprises: a plurality of LEDs couplable to form a plurality of segments of LEDs; a current sensor; and a controller to monitor a current level through an overall series LED current path, and to provide for first or second segments of LEDs to be in or out of the overall series LED current path at different current levels. The controller is configured to, in a first light emitting diode configuration, cause first and second segments of LEDs to be parallel to one another and in the overall series LED current path. The controller is further configured to, in a second light emitting diode configuration, cause first and second segments of light emitting diodes to be coupled in series and in the overall series light emitting diode current path.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 16, 2015
    Assignee: Point Somee Limited Liability Company
    Inventors: Anatoly Shteynberg, Dongsheng Zhou, Stephen F. Dreyer, Harlan Ohara, Sinan Doluca
  • Patent number: 8970251
    Abstract: Disclosed is a programmable logic device (PLD) which can undergo dynamic configuration at a high speed. The PLD includes a plurality of programmable logic elements (PLEs) and a switch for selecting electrical connection between the PLEs. The switch includes a plurality of circuit groups each of which includes first and second transistors. The second transistors of the circuit groups are electrically connected in parallel with one another. In each of the circuit groups, the electrical conduction between a source and a drain of the second transistor is determined based on configuration data held at a node between the gate of the second transistor and a drain of the first transistor, which allows the selection of the electrical connection and disconnection between the programmable logic elements by the selection of one of the circuit groups.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 8952725
    Abstract: A low voltage differential signal driving circuit including positive and negative differential output terminals, an automatic level selector, an output level detector and a transition accelerator. The positive and negative differential output terminals provide a transmission interface with a differential output signal for transmission of a data signal. The automatic level selector outputs a reference voltage corresponding to the transmission interface. The output level detector generates a low-high (or high-low) transition acceleration control signal based on the data signal, the reference voltage, and VTXP signal at the positive differential output terminal (or VTXN signal at the negative differential output terminal).
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: February 10, 2015
    Assignee: Via Technologies, Inc.
    Inventors: Yeong-Sheng Lee, Kuen-Chir Wang
  • Patent number: 8860312
    Abstract: A method for using an electronic ballast circuit configured to operate a high intensity discharge (HID) lamp. Multiple light emitting diodes (LEDs) are attached to the current output of the electronic ballast circuit, and current is driven from the current output to light said LEDs. Optionally, prior to driving current through the LEDs, the impedance of the current output is sensed; and the current is driven through the LEDs to light the LEDs upon detection of an impedance significantly lower than an impedance characteristic of the HID lamp. Ignition appropriate to ignite the high intensity discharge is not performed when LEDS are attached to the current output. Alternatively, a signal is provided to disconnect the LEDs during a high voltage output for ignition of the high intensity discharge (HID) lamp.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: October 14, 2014
    Assignee: Metrolight Ltd.
    Inventor: Jonathan Hollander
  • Patent number: 8823413
    Abstract: A device for sensing a binary signal includes a device configured to measure a signal level of the signal, a device configured to determine whether the measured signal level is “low” or “high”, a device configured to provide a variable input impedance, and a device configured to control the input impedance in response to the measured signal level. The variable input impedance may be provided by way of a transistor and a resistor, and by controlling the duty ratio of the transistor using pulse width modulation. Preferably, the input impedance is controlled to be low for low signal levels and to be high for high signal levels, which results in a more reliable sensing of binary signals. The device may be used for detecting the state of contact transducers suffering from parasitic resistances caused by moist and/or polluted environments. Further, a method of sensing a binary signal is provided.
    Type: Grant
    Filed: September 16, 2010
    Date of Patent: September 2, 2014
    Assignee: ABB Technology AG
    Inventors: Hans Björklund, Krister Nyberg, Tommy Segerbäck
  • Patent number: 8786202
    Abstract: A lighting device and a method of controlling a light emitted thereby are disclosed. A lighting device according to the present invention includes a rectifier unit configured to rectify an alternation current voltage to supply the rectified voltage to each of light emitting units, the light emitting units configured of a plurality of light emitting diodes connected with each other in series, a control unit configured to control each light emitting unit and a first switching element based on the input voltage and the first switching element configured to be switched on and off based on the control of the control unit, wherein the control unit controls to the first switching element switch on and off based on the input voltage to connect the first light emitting unit and the second light emitting unit alternatively in series and parallel.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 22, 2014
    Assignee: LG Electronics Inc.
    Inventor: Namjin Kim
  • Patent number: 8749268
    Abstract: An inverter-type high speed driver circuit having a first inverter branch and a second inverter branch wherein each of the inverter branches comprising a parallel circuit of a serial connection of a first impedance tuning unit and a respective first clocking transistor and a serial connection of a second impedance tuning unit and a respective second clocking transistor. The impedance tuning units are configured to adapt the conductivity of the respective inverter branch to set the output impedance of the driver circuit and each of the impedance tuning units is controlled in accordance with a data stream.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 10, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christian I. Menolfi, Thomas H. Toifl
  • Patent number: 8492985
    Abstract: A discharge lamp lighting apparatus has a configuration including a control unit which discriminates, for each polarity of an AC rectangular wave output, the output voltage detected with an output voltage detector for detecting the voltage applied to a discharge lamp, and carries out constant power control for each polarity separately. By thus detecting the output voltage for each polarity separately and by outputting a target current for each identical polarity, it can carry out constant power control positively even if the output voltage varies for each polarity, thereby being able to prevent current feedback to a different polarity, and to prevent power oscillation and partial reduction of electrodes due to an increase of the output voltage difference for each polarity.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: July 23, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Naohito Sato
  • Patent number: 8461875
    Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.
    Type: Grant
    Filed: February 18, 2011
    Date of Patent: June 11, 2013
    Assignee: SuVolta, Inc.
    Inventors: Scott E. Thompson, Lawrence T. Clark
  • Patent number: 8067962
    Abstract: A semiconductor integrated circuit device has a combinational logic circuit including one or plural logic cells connected in series. At least one of the logic cells includes a standard cell which includes a MIS transistor, an input terminal to which an output signal from a previous stage is inputted as an input signal, and an output terminal. A first conductivity-type first MIS transistor which is provided between the output terminal of the standard cell and a first power supply voltage, the first MIS transistor including a control terminal to which a circuit control signal is inputted, and the first MIS transistor supplying the first power supply voltage to the output terminal of the standard cell based on the circuit control signal in order to bring the standard cell into an operation-stopped state. A second conductivity-type second MIS transistor cuts off a leakage current of the MIS transistor in the standard cell.
    Type: Grant
    Filed: September 4, 2009
    Date of Patent: November 29, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tsuyoshi Nishikawa, Toshiyuki Furusawa
  • Patent number: 6549101
    Abstract: A plurality of resonators 50 are formed in a dielectric porcelain block 42, wherein each of the resonators 50 is formed by coating an interior surface of a through section with an interior conductor 54, thus constituting a dielectric filter 41. On a side surface 44 of the dielectric block 42 perpendicular to an open end face 43 having the through sections formed therein, there are formed protrusions 45 having a height L lower than that of the through sections. Terminal electrodes 60a and 60b are defined with the protrusions 45 taken as a boundary between the terminal electrodes 60a and 60b, and isolated from an exterior conductor 62.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: April 15, 2003
    Assignee: TDK Corporation
    Inventors: Masashi Gotoh, Kouji Tashiro
  • Patent number: 6362656
    Abstract: Output drivers preferably contain a plurality of driver circuits therein that are commonly connected to an output line to be driven and can be selectively enabled or disabled to increase or decrease drive capability, respectively. Driver circuits may include first and second control signal lines (e.g., MRS1, MRS2), a first pull-up/pull-down driver circuit having first and second data inputs, a first control input electrically coupled to the first control signal line (e.g., MRS1) and a second control input, and a second pull-up/pull-down driver circuit having first and second data inputs electrically coupled to the first and second data inputs of the first pull-up/pull-down driver circuit, respectively, a first control input electrically coupled to the second control signal line (e.g., MRS2) and a second control input. First and second complementary control signals lines (e.g.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: March 26, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-jae Rhee
  • Patent number: 6326811
    Abstract: An output buffer (200) having a protection circuit (228, 230, 232) which adjusts control of an output drive circuit (224, 226) in response to external voltages on the output pin (202). When the output pin is in a tri-state condition and receives an external voltage which is outside a predetermined voltage range, the protection circuit adjusts the voltage on the control gate of a transistor (224) in the output drive circuit. The protection circuit maintains the voltage across the transistor within the tolerance of the transistor. In one embodiment, the output drive circuit has pullup (204) and pulldown (206) portions. The output buffer provides a high voltage output driver having low voltage devices.
    Type: Grant
    Filed: September 11, 2000
    Date of Patent: December 4, 2001
    Assignee: Motorola Inc.
    Inventors: John Deane Coddington, Perry H. Pelley III
  • Patent number: 6087853
    Abstract: CMOS technology is used to create a controlled output impedance output buffer circuit. An output buffer driver uses buffer circuits having impedance elements with linear characteristics. A control circuit uses a known impedance load to control the impedance of the buffer circuits. The control circuit monitors a known current flowing through the known impedance load to determine whether the output buffer circuit's output impedance needs to be adjusted to match a transmission line's impedance. Adjustments occur when the control circuit generates control signals to turn on or off various buffer circuits (and their impedance elements) contained within the output driver. In doing so, the output buffer circuit ensures that its output impedance will match the impedance of a transmission line over the entire range of output voltages regardless of the variations caused by the manufacturing process, operation temperature and power supply voltage.
    Type: Grant
    Filed: June 22, 1998
    Date of Patent: July 11, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Carol A. Huber, Bernard L. Morris, Bijit T. Patel