Abstract: A polyphase decimation FIR filter apparatus including a modulo integrator circuit configured to integrate input samples and to provide integrated input samples; and a polyphase FIR filter circuit configured to process the integrated input samples, the polyphase FIR filter circuit including a plurality of multiplier accumulator circuits, each configured to accumulate products of coefficients and respective integrated signal samples, wherein each of the multiplier accumulator circuits receives a subset of FIR filter coefficients, wherein the FIR filter coefficients are derived as the nth difference of original filter coefficients, where n is a number of integrators in the integrator circuit, and wherein the FIR filter circuit is configured to perform computation operations with modulo arithmetic.

Abstract: Some embodiments present a method of performing a variable shift operation. This method can be used by a microprocessor that does not allow variable shift operation for certain operand sizes. The method simulates a shift instruction that shifts an operand by a shift count. The method identifies a first shift command and a second shift command. The method computes a mask value. The mask value depends on whether the shift count is less than half of the operand size or greater than or equal to half of the operand size. The method uses the mask value to cause one of the first shift command and the second shift command to produce no shift. In some embodiments, the method allows for the shift count to be specified in bytes or in bits.

Abstract: A unit status reporting protocol may also be used for context switching, debugging, and removing deadlock conditions in a processing unit. A processing unit is in one of five states: empty, active, stalled, quiescent, and halted. The state that a processing unit is in is reported to a front end monitoring unit to enable the front end monitoring unit to determine when a context switch may be performed or when a deadlock condition exists. The front end monitoring unit can issue a halt command to perform a context switch or take action to remove a deadlock condition and allow processing to resume.

Abstract: A data processing system and method. The data processing system includes a processor core that executes a program; a loop accelerator that has an array consisting of a plurality of data processing cells and executes a loop in a program by configuring the array according to a set of configuration bits; and a centralized register file which allows data used in the program execution to be shared by the processor core and the loop accelerator. The loop accelerator divides the configuration of the array into at least three phases according to whether data exchange with the central register file is conducted during the loop execution. Thus, unnecessary occupation of the routing resource, which is used for the data exchange between the loop accelerator and the central register file during the loop execution, can be avoided.

Abstract: A pipelined computer processor is presented that reduces data hazards such that high processor utilization is attained. The processor restructures a set of instructions to operate concurrently on multiple pieces of data in multiple passes. One subset of instructions operates on one piece of data while different subsets of instructions operate concurrently on different pieces of data. A validity pipeline tracks the priming and draining of the pipeline processor to ensure that only valid data is written to registers or memory. Pass-dependent addressing is provided to correctly address registers and memory for different pieces of data.

Abstract: Inter-processor communication systems and methods that define within the instruction set of the microprocessor a command for directing the microprocessor to relinquish control over at least one of the microprocessor's internal registers. The microprocessor may then signal a communication interface that collects data from external sources. The communication interface takes control over the internal register released by the microprocessor and inputs the collected external data directly into the internal register of the microprocessor. Once data is place into the internal register, control of that register may be returned to the microprocessor.

Abstract: A flexible results pipeline for a processing element of a parallel processor is described. A plurality of result registers are selectively connected to each other, to processing logic of the processing element and to a neighborhood connection register configured to receive data from and send data to other processing elements. The connections between the result registers and between the result registers and the neighborhood connection register are selectively configurable by applied control signals.

Abstract: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Abstract: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Abstract: A method and device for adaptively allocating reservation station entries to an instruction set with variable operands in a microprocessor. The device includes logic for determining free reservation station queue positions in a reservation station. The device allocates an issue queue to an instruction and writes the instruction into the issue queue as an issue queue entry. The device reads an operand corresponding to the instruction from a general purpose register and writes the operand into a reservation station using one of the free reservations station positions as a write address. The device writes each reservation station queue position corresponding to said instruction into said issue queue entry. When the instruction is ready for issue to an execution unit, the device reads out the instruction from the issue queue entry the reservation station queue positions to the execution unit.

Abstract: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.

Abstract: An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the sequencer circuit is operable, in a first environment, to cause the first predictor circuit to generate a prediction for a particular conditional branch op concurrently with the second predictor circuit generating a prediction for another particular conditional branch op, where the sequencer circuit is also operable, in a second environment, to cause the first predictor circuit to generate a prediction for the particular conditional branch op sequentially with the second predictor circuit generating a prediction for the another particular conditional branch operation.

Abstract: A processor according to the present invention cyclically executes a plurality of threads, for each time period allocated thereto. The processor stores, for each thread, configuration information of operation cells. Each of the threads (i) causes the execution of a different predetermined number of operation cells in series, and successively reconfigures an operation cell that has completed a last operation thereof in the time period allocated to a current thread, based on a stored piece of configuration information of the operation cell that corresponds to a next thread, and (ii) causes concurrent execution of an operation cell having a configuration for the current thread and an operation cell having a configuration for the next thread.

Abstract: Embodiments of the invention provide an apparatus of storing branch prediction information. In one embodiment, an integrated circuit device includes a first table for storing local branch prediction information, a second table for storing global branch prediction information, and circuitry. The circuitry is configured to receive a branch instruction and store local branch prediction information for the branch instruction in the first table. The local branch prediction information includes a local predictability value for the local branch prediction information. The circuitry is further configured to store global branch prediction information for the branch instruction in the second table only if the local predictability value is below a threshold value of predictability.

Abstract: A processor includes an instruction fetcher, a decoder, and an instruction processor. The instruction fetcher retrieves encoded machine-language instructions. The encoded machine-language instructions are encoded according to a predetermined key assigned only to the processor. The predetermined key is independent of opcodes of the processor. The decoder decodes each of the encoded machine-language instructions according to the predetermined key. The instruction processor executes the decoded machine-language instructions.

Abstract: A method, system and processor for increasing the instruction throughput in a processor executing longer latency instructions within the instruction pipeline. Logic associated with specific stages of the execution pipeline, responsible for executing the particular type of instructions, determines when at least a threshold number of the particular-type instructions is scheduled to be executed. The logic then automatically changes an execution cycle frequency of the specific pipeline stages from a first cycle frequency to a second, pre-established higher cycle frequency, which enables more efficient execution and higher execution throughput of the particular-type instructions. The cycle frequency of only the one or more functional stages are switched to the higher cycle frequency independent of the cycle frequency of the other functional stages in the processor pipeline.

Abstract: A processing system comprising processors and the dynamically configurable communication elements coupled together in an interspersed arrangement. The processors each comprise at least one arithmetic logic unit, an instruction processing unit, and a plurality of processor ports. The dynamically configurable communication elements each comprise a plurality of communication ports, a first memory, and a routing engine. For each of the processors, the plurality of processor ports is configured for coupling to a first subset of the plurality of dynamically configurable communication elements. For each of the dynamically configurable communication elements, the plurality of communication ports comprises a first subset of communication ports configured for coupling to a subset of the plurality of processors and a second subset of communication ports configured for coupling to a second subset of the plurality of dynamically configurable communication elements.

Abstract: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.

Abstract: A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target branch address is determined from a pre-programmed stored value and a branch to a sub-routine is performed in dependence upon a result of the comparison.

Abstract: A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring errors in the branch predictors and generate corrected behaviours for a prefetch unit 4.