Abstract: Electrolytic capacitor cells of paste electrode type are formed integrally in a composite or laminated belt in a predetermined pattern and subsequently severed or otherwise separated therefrom to provide a plurality of individual cells or stacked cell sets of desired shape. The belt includes at least one inner sheet of ion conducting/electron insulating material, outer sheets of electron conducting material, and intermediate sheets of insulating gasket material respectively interposed between the inner sheet and respective outer sheets. Each intermediate sheet has a plurality of holes arranged in a predetermined pattern and aligned with the holes in the other intermediate sheet for accommodating respective electrodes of a like number of pairs which have opposite surfaces in operative contact with the inner and respective outer sheets.

Abstract: In the manufacture of a semiconductor component, connection areas adapted to connect the component externally are formed by a metal array (3, 4) deposited on a conductive layer (6) of low melting point alloy, itself deposited on a metal temporary substrate (7). Each component chip (1) is placed in position and connected and then immobilized by means of a hardenable resin (5). The temporary substrate (7) is then removed by melting the alloy layer (6) to expose the surfaces of the connection areas (3, 4) for making external electrical and/or thermal connections to the encapsulated component.

Abstract: A method for forming a field effect transistor having a submicron gate length. A gate electrode is formed by angularly depositing metal through an aperture formed in a thick masking layer. A substrate upon which the gate electrode is to be formed is placed in an apparatus for depositing a stream of evaporated metal through the aperture onto portions of the substrate surface exposed by the aperture. The stream is directed at a selective oblique angle .theta. with respect to a normal to the surface of such substrate. Portions of the exposed surface of the substrate are shadowed from the obliquely directed stream of evaporated metal by an edge of the aperture formed in the thick masking layer. Thus, only selected portions of such obliquely directed stream of evaporated metal are deposited onto unshadowed portions of the substrate to thereby provide the gate electrode.

Abstract: A high-density electronic package module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, each access plane is etched to cut back the semiconductor material then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Abstract: A resin mold type semiconductor device comprising molded articles for sealing, each consisting of a resin material and having a gap portion thereinside; a semiconductor element positioned in said gap portion inside said molded article for sealing, said seminconductor element having electrodes; electrically conductive leads, each positioned in said gap portion of said molded article for sealing and having one end thereof protruding outwardly from said molded article for sealing; wires, each electrically connecting said electrode of said seminconductor element to said lead; and an insulation material covering at least the surface of said semiconductor element.

Abstract: The method of reduction comprises two successive steps. The first step consists in forming an electrolyte layer at the surface of the layer to be reduced which is an oxidized surface layer of a substrate. During the second step, the layer is reduced through the layer of electrolyte which is an ionic conductor for the ionizing species. The second step is carried out in a first variant by thermal reduction in a reducing atmosphere and in a second variant by exposure to a reducing plasma.

Abstract: A porous sintered body for an aluminum-titanium alloy electrolytic capacitor has a wire of nitrogenized titanium, or the like, implanted therein. A method of producing such a porous body subjects a titanium wire to a nitriding treatment, and embeds the nitrogenized Ti wire into a press-molded body of the mixture of aluminum and either titanium or titanium hydride powders. Then, the press-molded body is sintered. An excellent LC characteristic is obtained even under the sintering condition, and the aluminum-titanium electrolytic capacitor is devoid of bent lead wires.

Abstract: Aluminum metal runs and bonding pads on an integrated circuit die are passivated, subsequent to wire bonding of the circuit die to a lead frame, by immersing the lead frame and wire-bonded die in hot deionized water for approximately 60 minutes.

Abstract: The present invention is directed to a thyristor self-protected against overvoltage by the avalanche mechanism, the protection resulting from a well cut in the top surface of the thyristor and extending through one base region of the thyristor and forming two regions of opposite conductivity type at the bottom of said well, and to the process for making the thyristor.

Abstract: A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed.

Abstract: The present invention is directed to a thyristor self-protected against overvoltage by the avalanche mechanism, the protection resulting from a laser scribed ring shaped groove cut in the top surface of the thyristor and extending into one base region of the thyristor whereby the forward blocking junction is contoured toward the reverse blocking junction under the ring shaped groove, and to the process for making the thyristor.

Abstract: A system of identifying each chip with identification data that is both human and machine readable. The chip identification is then used in sorting, storing, testing, assembling and failure analysis. The identification usage at these process steps eliminates chip part number mix-up and placement. It provides data used for quality control.

Abstract: A process for making stacked high voltage rectifiers includes initially doping a plurality of silicon wafers with paint-on dopants applied with an applicator that is gradually moved from the center to the outer edge of each wafer while the wafer is peripherally supported and rotated sufficiently slowly to prevent spin-off and runover of each dopant onto the reverse side of the wafer. The dopants are driven in by heating in a diffusion furnace. The same slow rotation and moving applicator technique then is used to coat only the N-doped side of the wafer with a paint-on noble metal dopant. The noble metal is driven in using a diffusion furnace at a temperature that is selected in accordance with the measured reverse recovery time of the wafer prior to noble metal diffusion.The wafers are silver coated and stacked, and a compression jig is used to exert compressive force on the stack while it is heated in a alloying furnace to a temperature sufficiently high to cause "wetting" of the silver.

Abstract: A method of manufacturing a monolithically integrable circuit, which includes depositing an SiO.sub.2 layer on the surface of a semiconductor substrate containing p-n junctions of the circuit, at least partially covering the SiO.sub.2 layer with a first metallization supported by the SiO.sub.2 layer and containing conductor runs and electrodes capacitively coupled to the surface of the semiconductor substrate through the SiO.sub.2 layer, directly covering the first metallization with a sputtered-on SiO.sub.2 insulating layer after the first metallization is completed, covering the sputtered-on SiO.sub.2 layer with a further inorganic insulating layer generated by the plasma method, structuring the further inorganic insulating layer and the sputtered-on SiO.sub.2 layer, forming cutouts in the further inorganic insulating layer and the sputtered-on SiO.sub.

Abstract: A method of fabricating a semiconductor integrated circuit by providing a semiconductor body having a major surface; depositing a first layer of a conductive material on the major surface of the semiconductor body, and depositing a layer of a refractory silicide on the first layer of conductive material. Portions of said refractory silicide layer are marked to define a first pattern thereon; and the silicide layer is etched down to the first conductive layer in order to produce the pattern defined by the masking step. Portions of the body are masked again to define a second pattern thereon; etching said first conductive layer in said second masking pattern. The semiconductor body is sintered to stabilize the contact between first conductive layer and layer of refractory silicide. A layer of dielectric material is deposited on body. Portions of said dielectric material are masked to define a third pattern thereon; and the dielectric material is etched to silicide layer in accordance with the third pattern.

Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process of two metal depositions to increase step or sidewall coverage. After a first layer of metal is deposited, a preferential etch removes all of the metal except on the vertical sides of steps or apertures. A second layer of metal is deposited over the remaining parts of the first, resulting in smoother transistions and greater thickness at steps.

Abstract: The present invention provides for a method for manufacturing a charge storage region in a semiconductor substrate for a memory cell in a dynamic RAM, comprising forming an insulating layer on the substrate, forming a masking layer over the insulating layer, forming at least one aperture in the masking layer, the aperture defining the charge storage region in the semiconductor substrate, implanting dopant ions of a first polarity through the aperture for diffusion through the substrate, and implanting dopant ions of a second polarity through the aperture for diffusion through the substrate to a lesser degree than the first polarity dopant diffusion so that the diffusion of the first polarity dopant with respect to the diffusion of the second polarity dopant forms a P-N junction substantially aligned with the edge of the masking layer aperture to define the periphery of the charge storage region.

Abstract: A method for preparing an electrochromic display device comprising first and second electrochromic layers and a solid electrolyte interposed therebetween, comprises the steps of forming a conductive film on a substrate, forming an insulating film, over the entire surface of the conductive film forming a resist at portions on the insulating film other than a display pattern and lead-in electrodes, removing the insulating film at the display pattern and the lead-in electrodes, forming the electrochromic material layers and the solid electrolyte over the entire portions other than the lead-in electrode, removing the resist and the electrochromic layers and the solid electrolyte as formed on the insulating film, and forming a second electrode on the second electrochromic layer.

Abstract: A process for fabricating semiconductor devices including a field effect transistor has been described incorporating a substrate, a layer of thermal oxide having windows, a layer of polycrystalline silicon to form the gate electrode of field effect transistors and a first interconnection layer, a layer of silicon nitride, a layer of phosphorous doped silicon dioxide which have windows larger than the device windows and which is reflowed to smooth its upper surface over the polysilicon interconnections and to provide round edges, impurity regions formed on either side of the silicon gate electrode and bounded by the thermal oxide, forming openings to the drain and source regions, depositing a layer of metal over the substrate and defining the layer of metal to form a second layer of interconnections and also to provide ohmic contact to the source and drain regions.

Abstract: A field effect transistor has improved punch-through resistance by the implantation of a dose of ions through the center of the active area. The energy of the dose is such that the ion concentration peaks at the depth most susceptible to punch-through. The threshold voltage of the transistor is set by the combination of a lower than normal threshold implant and the tail concentration of the blocking implant.