Abstract: A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by the memory configuration information stored in control registers. A cache hit detection circuit includes an address register storing the data access address, tag memories storing tag data of the data access address, a data processing device selectively outputting the tag data or an adjusted tag data as processed data according to a direct address signal, and address comparators each comparing the processed data with portion bits of the data access address from the address register, and outputting an address match signal as comparison match. The tag data is adjusted to a predetermined address by the data processing device, which is the highest address of memory space of the processor.

Abstract: Methods and systems for maintaining cache consistency are described. A group of instructions is executed. The group of instructions can include multiple memory operations, and also includes an instruction that when executed causes a cache line to be accessed. In response to execution of that instruction, an indicator associated with the group of instructions is updated to indicate that the cache line has been accessed. The cache line is indicated as having been accessed until execution of the group of instructions is ended.

Abstract: A memory controller is connected with a first memory requiring refresh and a second memory not requiring refresh, both of which share part of a bus, comprising: a first memory controller that conducts access control and auto-refresh control for the first memory; a second memory controller that conducts access control for the second memory; and an arbiter that adjusts the timing of outputting a signal generated for the first memory and another signal generated for the second memory to a bus, wherein, with a judgment that the signal from the first memory controller is an auto-refresh request, a refresh request signal for the first memory is outputted even while the second memory is being accessed.

Abstract: A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=log2M. The K layers M/2 decision cells of a first layer to indicate the other one of the respective two of the M cache entries and to transmit a hit signal in response to the signal, a second layer of M/4 decision cells to enable the other one of the respective two of the M/2 decision cells of the first layer and transmit a second hit signal in response to the signal, a (K?1)th layer of two decision cells to enable the other one of the respective two decision cells of the (K?2)th layer and transmit a third hit signal in response to the second hit signal, and a Kth layer of a root decision cell to enable the other one of the respective two decision cells of the (K?1)th layer in response to the third hit signal.

Abstract: A method for maximizing page locality within a networking system operationally attached to a plurality of processing entities wherein each processing entity either shares or includes a corresponding memory hierarchy wherein each memory hierarchy has a table of pages temporally managed by access from the networking system is disclosed. The method includes providing at least one memory access channel to each memory hierarchy and moving information to and from pages in the memory hierarchy of a particular processing entity via its associated memory access channels.

Abstract: The present invention provides a processor including: a plurality of memory banks; a read-address generation circuit for supplying a read address to each of the memory banks on the basis of a read-register specification and a read-register scan direction; a read control circuit for executing control to rearrange a plurality of pieces of read data, which is read out from the memory banks in accordance with the read addresses, on the basis of the read-register specification and a read-register displacement; and a processing unit for carrying out a plurality of operations on the rearranged pieces of read data output by the read control circuit.