Patents Examined by Alan Otto
  • Patent number: 11886361
    Abstract: A memory controller having an improved operating speed controls a memory device in response to a request from a host. The memory controller includes: a processor for driving firmware for controlling communication between the host and the memory device; a map data receiver for receiving map data including a plurality of mapping entries including physical block addresses, for operations to be performed on the memory device from the memory device under the control of the processor; and a map data controller for checking a mapping entry corresponding to the request, which are received from the map data receiver, snooping the detected mapping entry and outputting the detected mapping entry to the processor.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: January 30, 2024
    Assignee: SK hynix Inc.
    Inventors: Young Jo Kim, Sung Yeob Cho
  • Patent number: 11847052
    Abstract: A method of memory allocation in a host computer includes: allocating one or more regions of physical working memory for use by an application, the regions individually including contiguous physical memory segments, but the regions not necessarily being contiguous between themselves; generating a segment address table having at least as many entries as the total number of physical memory segments allocated to the application; populating entries of the segment address table sequentially and contiguously with the physical addresses of the physical memory segments across the or each region in order; presenting to the application a contiguous virtual addressable space having at least as many virtual memory segments as the total number of physical memory segments allocated to the application; and mapping from virtual memory addresses to physical memory addresses by reference to the segment address table.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 19, 2023
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Paul Bowen-Huggett
  • Patent number: 11836090
    Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partitions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, all of the disjointed range partitions are deleted. A first new cached partition range that contains the data value is created; it excludes at least one value that had been cached. The remaining values are placed in uncached range partitions; contents of the cache are updated to reflect the new range partition.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: December 5, 2023
    Assignee: Kinaxis Inc.
    Inventor: Angela Lin
  • Patent number: 11762581
    Abstract: A method, device, and system for controlling a data read/write command in an NVMe over fabric architecture. In the method provided in the embodiments of the present disclosure, a data processing unit receives a control command sent by a control device, the data processing unit divides a storage space of a buffer unit into at least two storage spaces according to the control command sent by the control device, and establishes a correspondence between the at least two storage spaces and command queues, and after receiving a first data read/write command that is in a first command queue and that is sent by the control device, the data processing unit buffers, in a storage space that is of the buffer unit and that is corresponding to the first command queue, data to be transmitted according to the first data read/write command.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: September 19, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Victor Gissin, Xin Qiu, Pei Wu, Huichun Qu, Jinbin Zhang
  • Patent number: 11733932
    Abstract: Example implementations relate to managing data on a memory module. Data may be transferred between a first NVM and a second NVM on a memory module. The second NVM may have a higher memory capacity and a longer access latency than the first NVM. A mapping between a first address and a second address may be stored in an NVM on the memory module. The first address may refer to a location at which data is stored in the first NVM. The second address may refer to a location, in the second NVM, from which the data was copied.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 22, 2023
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Gregg B Lesartre, Andrew R Wheeler
  • Patent number: 11734185
    Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective partitions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, the range of the target range partition is reduced until either: the data value is excluded (if the data value is an end point of the partition range); or elements within the target range are evicted to make space for the data value.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: August 22, 2023
    Assignee: Kinaxis Inc.
    Inventor: Angela Lin
  • Patent number: 11726906
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, address translation unit, generation unit, and reception unit. The nonvolatile memory includes erase unit areas. Each of the erase unit areas includes write unit areas. The address translation unit generates address translation information relating a logical address of write data written to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory. The generation unit generates valid/invalid information indicating whether data written to the erase unit areas is valid data or invalid data. The reception unit receives deletion information including a logical address indicative of data to be deleted in the erase unit area.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11714758
    Abstract: A method to store a data value onto a cache of a storage hierarchy. A range of a collection of values that resides on a first tier of the hierarchy is initialized. The range is partitioned into disjointed range partitions; a first subset of which is designated as cached; a second subset is designated as uncached. The collection is partitioned into a subset of uncached data and cached data and placed into respective portions. The range partition to which the data value belongs (i.e. the target range partition) is identified as being cached. If the cache is full, the target range partition is divided into two partitions, the partition that excludes the data value is designated as uncached; the values therein are evicted. If the cache has space, the data value is copied onto the cache; otherwise the division/eviction are repeated until the cache has space.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: August 1, 2023
    Assignee: Kinaxis Inc.
    Inventor: Angela Lin
  • Patent number: 11681443
    Abstract: A data storage system includes a head node and mass storage devices. The head node is configured to store volume data and flush volume data to the mass storage devices. Additionally, the head node is configured to determine a quantity of data partitions and/or parity partitions to store for a chunk of volume data being flushed to the mass storage devices in order to satisfy a durability guarantee. For chunks of data for which complete copies are also stored in an additional data storage system, the head node is configured to reduce the quantity of data partitions and/or parity partitions stored such that required storage space is reduced while still ensuring that the durability guarantee is satisfied.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: June 20, 2023
    Assignee: Amazon Technologies, Inc.
    Inventors: Sriram Venugopal, Kun Tang, Norbert Paul Kusters, Jianhua Fan
  • Patent number: 11640257
    Abstract: In a data processing method, a worker node in a distributed data processing system receives first data from an upstream worker node. The first data has been stored in a buffer of the upstream worker node. The worker node sends a first portion of the first data to a persistent storage device of the distributed data processing system for persistent backup, and performs computational processing on the first data to generate second data. Prior to completing performing computational processing on the first data, the worker node sends acknowledgement information to the upstream worker node to instruct the upstream node to delete the first data from the buffer of the upstream worker node. The worker node then sends the second data to a downstream worker node in the distributed data processing system for further processing by the downstream worker node.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: May 2, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Cheng He, Qun Huang, Pak-Ching Lee
  • Patent number: 11630595
    Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for efficiently storing data. The methods include segmenting a parcel of data into one or more data chunks according to a physical block size of the secondary storage unit, wherein the one or more data chunks include a partial data chunk and zero or more full data chunks; sending each full data chunk of the zero or more full data chunks to the secondary storage unit to be written to a selected physical block of the secondary storage unit; collecting, in a collection buffer, the current partial data chunk and at least another partial data chunk; and sending a combination of the current partial data chunk and a subset of the plurality of other partial data chunks to the secondary storage unit to be written to a selected physical block of the secondary storage unit, wherein said combination fills substantially all of a physical-block-sized data chunk.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 18, 2023
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11531489
    Abstract: A system-on-chip includes a first intellectual property (IP) generating a plurality of request packets; and a second IP generating a plurality of response packets based on the plurality of request packets, wherein the second IP includes a plurality of processing elements processing the plurality of request packets and generating the plurality of response packets; a distributer, when the plurality of request packets are input from the first IP, determining a scheduling policy based on a packet type of the plurality of request packets and distributing the plurality of request packets to the plurality of processing elements according to the determined scheduling policy; and an aggregator, when the plurality of response packets are received from each of the plurality of processing elements, aggregating the plurality of response packets according to the determined scheduling policy.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: December 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinwoo Kim, Jaeyong Jeong, Myunghyun Jo, Wonhee Cho
  • Patent number: 11507461
    Abstract: Techniques providing I/O control involve: in response to receiving an I/O request, detecting a first set bits for a stripe in a RAID. The RAID is built on disk slices divided from disks. The stripes include extents. Each of the first set bits indicates whether a disk slice where a corresponding extent in the stripe is located is in a failure state. The techniques further involve determining, from the stripe and based on the first set bits, a first set of extents in the failure state and a second set of extents out of the failure state. The techniques further involve executing the I/O request on the second set of extents without executing the I/O request on the first set of extents. Such techniques can simplify storage bits in I/O control, support the degraded stripe write request for the RAID and enhance performance executing the I/O control.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Geng Han, Jianbin Kang, Jibing Dong
  • Patent number: 11500572
    Abstract: The present disclosure provides methods, systems, and non-transitory computer readable media for optimizing performance of a data storage system. The methods include receiving an I/O request to write a payload of data; selecting one or more secondary storage units from a plurality of secondary storage units coupled to the data storage system, wherein the selection of the one or more secondary storage units is based on an assessment of one or more effects on the garbage collection activity of the plurality of secondary storage units predicted to result from storing the payload of data on the plurality of secondary storage units; and storing the payload of data on the one or more selected secondary storage units.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Alibaba Group Holding Limited
    Inventor: Shu Li
  • Patent number: 11500737
    Abstract: A network element includes multiple ports configured to communicate over a network, a buffer memory, a snapshot memory, and circuitry. The circuitry is configured to forward packets between the ports, to temporarily store information associated with the packets in the buffer memory, to continuously write at least part of the information to the snapshot memory concurrently with storage of the information in the buffer memory, and, in response to at least one predefined diagnostic event, to stop writing of the information to the snapshot memory, so as to create in the snapshot memory a coherent snapshot corresponding to a time of the diagnostic event.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: November 15, 2022
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Niv Aibester, Shmuel Shichrur, Barak Gafni
  • Patent number: 11494100
    Abstract: According to embodiments of the present disclosure, a method, device and computer program product for storage management are proposed. The method comprises: obtaining, in a first virtual storage device, a first portion storing a source file, the source file being used to update a target file; determining a second portion in the first virtual storage device, data stored in the second portion being changed relative to data stored in a second virtual storage device, the data stored in the second virtual storage device including the target file; determining a changed portion based on the first portion and the second portion, the changed portion indicating changed data of the source file relative to the target file; and updating the target file based on the changed portion. Therefore, the present solution can reduce data transmission and resource consumption.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: November 8, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mengze Liao, Jing Yu, Ming Zhang, Yongsheng Guo, Jin Ru Yan
  • Patent number: 11442860
    Abstract: When a read request for the data portion is received from an application executing on a host, the host may determine whether the data portion is in host cache, and if so, whether the logical storage unit of the data portion is shared by another host system. If there is another host system sharing the logical storage unit, a latest version stored on the storage system may be determined and compared to the version stored in the host cache. If the version in the host cache is the same as the latest version stored on the storage system, the data portion may be retrieved from the host cache. If the version in the host cache is not the latest version stored on the storage system, the data portion may be retrieved from the storage system, and the host cache may be updated with the latest version of the data portion.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: September 13, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Michael J. Scharland, Ian Wigmore, Arieh Don
  • Patent number: 11429298
    Abstract: A non-volatile dual in-line memory module (NVDIMM) instantiates first and second partitions of non-volatile memory. The first partition is reserved and is not accessible to an operating system, and the second partition is accessible to the operating system. A processor may generate information uniquely associated with an information handling system and write the information to the first partition.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: August 30, 2022
    Assignee: Dell Products L.P.
    Inventors: Hung-Tah Wei, Sundar Dasar
  • Patent number: 11354057
    Abstract: A storage device includes a main storage including a plurality of nonvolatile memory devices, the main storage device configured to store data; and a storage controller configured to control the main storage. The storage controller is configured to, divide a plurality of memory blocks of the plurality of nonvolatile memory devices into a plurality of banks, assign each one of the plurality of banks into one of a) a plurality of sets and b) one free bank, each of the plurality of sets including at least one bank, perform data migration operation to transfer the data among the sets by using the one free bank in response to an input/output (I/O) request from an external host device while securing a specific I/O execution time, and control the data migration operation such that the I/O request is independent of the data migration operation.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: June 7, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byoung-Geun Kim, Jae-Yoon Choi, Joo-Young Hwang
  • Patent number: 11307937
    Abstract: A method, computer program product, computer system, and the like that provide for the efficient reclamation of storage space in a deduplication system are disclosed. The method, for example, includes identifying one or more storage constructs of a number of storage constructs and generating an indication that a reclamation operation is to be performed with respect to the one or more storage constructs. In an embodiment, each of the plurality of storage constructs includes metadata and a number of units of data. The one or more storage constructs are identified, at least in part, by determining that a portion of the number of units of data of each of the one or more storage constructs is in a state, wherein the determining is based, at least in part, on at least a portion of the metadata.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 19, 2022
    Assignee: Veritas Technologies LLC
    Inventors: Shuai Cheng, Xianbo Zhang