Patents Examined by Albert Li
  • Patent number: 11226864
    Abstract: A method of collecting error logs according to the disclosure includes generating, during procedure of BIOS of a server, at least one BIOS error log based on detection of an error condition of one or more of hardware devices and a CPU, transmitting the at least one BIOS error log to a BMC, storing the at least one BIOS error log received from the CPU, packaging the at least one BIOS error log and at least one log that is generated by the BMC and that is related to BMC sensors to generate an error log file, and storing the error log file.
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: January 18, 2022
    Assignee: Jabil Circuit (Shanghai) Co., Ltd.
    Inventors: Chin Liang, Yen-Cheng Chang, Shuo-Hung Hsu
  • Patent number: 11221926
    Abstract: An information processing system includes a plurality of information processing apparatuses each of which includes hardware, a control processor, and a switch circuit wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected, a first switch circuit in the first information processing apparatus is configured to generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses, a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line, and the second control processor is configured to acquire information transmitted from the first hardware via the signal line.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: January 11, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Tatsuya Yamana, Reo Tajima
  • Patent number: 11216348
    Abstract: The present invention provides a control method of a server, wherein the control method includes the steps of: periodically controlling a first register and a second register of a first node to have a first value and a second value, respectively; periodically controlling a third register and a fourth register of a second node to have a third value and a fourth value, respectively; controlling the first register and the fourth register to synchronize with each other, wherein the first value is different from the fourth value; controlling the second register and the third register to synchronize with each other, wherein the second value is different from the third value; and periodically checking if the third register has the third value and the fourth register has the fourth value to determine if the first node fails to work.
    Type: Grant
    Filed: January 24, 2021
    Date of Patent: January 4, 2022
    Assignee: Silicon Motion, Inc.
    Inventor: Li-Sheng Kan
  • Patent number: 11194682
    Abstract: Architectures and techniques are described that can enhance the functionality of a witness for an active-active storage array. In the event of a dual storage area network (SAN) failure, or another suitable event, host-array connectivity can take precedence for the witness in determining a winner or loser. Techniques are presented to identify connectivity issues and to utilize connectivity data in connection with determining a winner or a loser.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: December 7, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Deepak Vokaliga, Svetlana Sokolova
  • Patent number: 11182250
    Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for resynchronizing data in a storage system. One of the methods includes determining that a particular disk of a capacity object of a storage system is out-of-sync and that a primary disk is unavailable; and for each segment of one or more segments of the capacity object: generating a first version of the column of the segment corresponding to the unavailable primary disk; determining whether the data integrity token in the column summary of the generated first version is valid; and in response to determining that the data integrity token is valid, resynchronizing the column of the segment corresponding to the particular disk using i) the primary columns of the segment corresponding to each available primary disk and ii) the first version of the column of the segment corresponding to the unavailable primary disk.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: November 23, 2021
    Assignee: VMware, Inc.
    Inventors: Enning Xiang, Wenguang Wang, Vamsi Gunturu
  • Patent number: 11176006
    Abstract: A method of reconfiguring an addressing mechanism in a system-on-chip comprising system circuitry and monitoring circuitry having tree-structured units for routing communications through the system, includes sending a discovery message, receiving discovery responses from the units, each discovery response identifying the number of individually addressable entities in that unit and those units in the branch above that unit; in response to not receiving a response from one or more units, determining that one of those units is defective; enabling a crosslink between a first unit in the same branch as the defective unit and a second unit in an adjacent branch; sending a further discovery message; receiving a further discovery response from the second unit identifying the number of individually addressable entities in that second unit, those units in the branch above that second unit, the first unit, and those units in the branch above the first unit; and reconfiguring the address of the crosslink so as to cause a
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: November 16, 2021
    Assignee: SIEMENS INDUSTRY SOFTWARE INC.
    Inventor: Callum Stewart
  • Patent number: 11169892
    Abstract: Embodiments herein describe a hardware solution where a reset monitor in an integrated circuit detects and reports unintentional resets. A glitch in a reset path can cause a logic block to initiate an undesired or unintentional reset. As a result, the local circuitry in the logic block resets which causes them to lose data and their current state. In the embodiments herein, the reset monitor can monitor the reset signals generated within the logic blocks in the circuit. The reset monitor can compare these reset signals to golden copies of the resets signals generated by the reset generator. If a reset signal generated within a logic block does not match the corresponding golden copy of the reset signal, the reset monitor determines that an unintentional reset has occurred.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: November 9, 2021
    Assignee: XILINX, INC.
    Inventors: Sarosh Azad, Akshay Shetty, Alex Warshofsky
  • Patent number: 11163633
    Abstract: An application monitoring device that includes a memory operable to store an application and a fault detection engine implemented by a processor. The fault detection engine is configured to obtain a set of application metric values for the application. Each application metric value indicates a performance level of the application. The fault detection engine is further configured to compare each application metric value to a set of application metric value ranges and to determine a performance status value for each application metric value based on the comparison. The fault detection engine is further configured to determine a warning level for the application and to determine that the warning level exceeds the fault detection threshold value. The fault detection engine is further configured to trigger an alert indicating a fault has been detected in the application in response to the determination.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: November 2, 2021
    Assignee: Bank of America Corporation
    Inventors: Sunil R. Bangad, Praveen Kumar Kasu, Akashkumar V. Desai
  • Patent number: 11163659
    Abstract: Embodiments may include apparatus, systems, and methods associated with an Enhanced Serial Peripheral Interface (eSPI) channel interface to couple to a data bus to link an eSPI primary device to an eSPI secondary device. In embodiments, the eSPI primary device includes an eSPI device controller and is coupled to the channel interface and transmits a notification of a crash event, e.g., a catastrophic error (CATERR), via packet-based signaling, such as a virtual wire (VW) over the data bus to allow the eSPI primary device to transmit the notification of the crash event without allocation of a dedicated wire signal for the notification between the eSPI primary device and the eSPI secondary device. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: November 2, 2021
    Assignee: Intel Corporation
    Inventors: Aditya Bhutada, Zhenyu Zhu, Mazen Gedeon
  • Patent number: 11119873
    Abstract: A processor comprises a plurality of processing units, wherein there is a fixed transmission time for transmitting a message from a sending processing unit to a receiving processing unit, based on the physical positions of the sending and receiving processing units in the processor. The processing units are arranged in a column, and the fixed transmission time depends on the position of a processing circuit in the column. An exchange fabric is provided for exchanging messages between sending and receiving processing units, the columns being arranged with respect to the exchange fabric such that the fixed transmission time depends on the distances of the processing circuits with respect to the exchange fabric. The processor comprises at least one delay stage for each processing circuit and switching circuitry for selectively switching the delay stage into or out of a communication path involved in message exchange.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: September 14, 2021
    Assignee: GRAPHCORE LIMITED
    Inventor: Stephen Felix
  • Patent number: 11119858
    Abstract: In general, the invention relates to a method for managing data. The method includes detecting a failure of a persistent storage device of a plurality of persistent storage devices, and in response to the detecting, initiating a rebuilding of data in a spare persistent storage device using proactive copy metadata, checkpoint metadata, and slice metadata, wherein the data is a copy of data that was stored in the persistent storage device.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: September 14, 2021
    Assignee: DELL PRODUCTS L.P.
    Inventors: Dharmesh M. Patel, Ravikanth Chaganti, Rizwan Ali
  • Patent number: 11093321
    Abstract: An information handling system includes a management controller that receives a notification associated with a stop error, captures a screenshot that includes a matrix bar code associated with the stop error, and scans the matrix bar code to retrieve a stop code corresponding to the stop error. If a component associated with the stop error is not updated, then an update for the component may be downloaded to a non-volatile storage device. An update table is generated that includes a location of the update in the non-volatile storage device; and on reboot the update table may be read to determine the location of the update.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: August 17, 2021
    Assignee: Dell Products L.P.
    Inventors: Palani Raja Zeavelou, Santosh Gore, Raveendra Babu Madala
  • Patent number: 11086726
    Abstract: User-based recovery point objectives (RPOs) for disaster recovery are described herein. A method as described herein can include obtaining, by a device operatively coupled to a processor, transient information associated with a file stored by a data storage system; determining, by the device, whether the transient information associated with the file indicates that a condition for replicating the file has been met; and inserting, by the device, the file into a replication queue associated with the data storage system in response to a positive result of the determining.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 10, 2021
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Shiv Shankar Kumar, Jai Prakash Gahlot
  • Patent number: 11061785
    Abstract: Systems and methods for a service based disaster recovery system are disclosed. Embodiments may include the ability to configure and deploy a DR environment, including providing the ability to configure a DR service in the DR environment for one or more deployed primary services in a primary environment. An environment management database holds DR configuration data including the status of the deployed services. An environment manager may interact with the environment management database to determine an associated action for the services. The services may perform activation (e.g., wake up) or enter a standby mode (e.g., sleep) depending on the determined action.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 13, 2021
    Assignee: SailPoint Technologies, Israel Ltd.
    Inventors: Shlomi Wexler, Itay Maichel, Shachar Radoshinsky
  • Patent number: 11003554
    Abstract: Techniques for providing metadata (and/or data) protection in a data storage system. The techniques can include storing, for a specific data page, two (2) instances of a main metadata page and one (1) instance of a corresponding alternative metadata page in a protected storage object referred to herein as the “2+1-way mirror”. For the specific data page, two (2) instances of a main metadata page can be stored on a first drive and a second drive, respectively, of the 2+1-way mirror such that the first and second drives each have a copy of the same main metadata page. Further, an instance of a corresponding alternative metadata page can be stored on a third drive of the 2+1-way mirror. The 2+1-way mirror provides protection against metadata loss due to the concurrent failure of two (2) physical drives, and further provides protection against catastrophic metadata errors and/or inconsistencies due to software failures.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: May 11, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Vladimir Shveidel, Uri Shabi, Ronen Gazit, Alex Soukhman
  • Patent number: 10990486
    Abstract: A technique for repairing an indirect addressing structure of a file system damaged by corruption of a mid-level mapping (MID) page includes scanning selected leaf pages to identify leaf pages associated with the corrupted MID page, then recreating the MID page by recreating pointers to the identified leaf pages. The scanning includes (1) based on an association of groups of leaf pages with corresponding sets of families of storage objects, scanning the leaf pages of only those groups of leaf pages associated with the family of storage objects for the corrupted MID page. The scanning further includes (2) performing a two-pass process including first identifying all leaf pages for the logical offset range of the corrupted MID page and then pruning those identified leaf pages that are reachable via non-corrupted MID pages, yielding the leaf pages for the corrupted MID page only, usable to recreate the corrupted MID page.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: April 27, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Kumari Bijayalaxmi Nanda, Dixitkumar Patel, Soumyadeep Sen, Rohit K. Chawla, Alexander S. Mathews