Abstract: A diagnostic method enables a determination of which of a plurality of data processing modules is at fault in a chain of data processing modules extending between an input and an output. The method includes the steps of reinputting a user (e.g., test) file that has failed to print, to a diagnostic software module which appends a diagnostic indicator to the test file. The diagnostic module and the remaining data processing modules are then operated to process the test file from the input to the output. The diagnostic module monitors operations of the data processing modules and forces one of the data processing modules that is intermediate a first module in the chain and a last module in the chain, to respond to the diagnostic indicator by writing processed results of the test file into a memory file. The diagnostic module then determines if the memory test file exists and, if yes, further checks operations of data processing modules which lie between the intermediate module and the output.

Abstract: A method of determining the reliability of data transmission system links is comprised of transmitting a data stream containing a data integrity sequence and at least one accumulated error count sequence along one of the links, determining the integrity of the data in the stream at the end of the link using the data integrity sequence, adding a count of data errors detected to the accumulated error count sequence, and periodically detecting the count as a measure of the reliability.

Abstract: Hierarchical Test Subsequence (TS) subgraphs and Finite State Machine (FSM) subgraphs are merged.Hierarchical FSM subgraphs are merged (82) by connecting FSM model (33) child subgraph transitions or graph edges with states or vertices in the FSM parent subgraph. Matching is done based on Input/Output sequences. This merging (82) is repeated until all FSM child subgraphs are merged into FSM childless subgraphs. FSM childless subgraphs are Merged FSM graphs (83).Hierarchical Test Subsequence (TS) subgraphs (65) are merged (38) by finding peer subgraphs for TS child subgraphs. TS micro-edges from module entry and to module exit are connected to peer level FSM model states or vertices identified by matching Input/Output sequences. This merging (38) is repeated until all TS child subgraphs are merged into TS childless subgraphs. TS childless subgraphs are Merged TS graphs (39).

Abstract: A system for detecting and locating errors in printed wire assemblies contained in a device with capabilities of performing a power on self test (POST) comprised of testing subroutines. The system monitors the device during execution of the POST. If a run error occurs during the POST, the system, through its monitoring, receives an indication of the run error. The system then delivers to the device a command, external to the POST routine, which directs the POST routine to thereafter separately execute each of the testing subroutines of the POST. If a run error occurs in any testing subroutine as it is being separately executed, a signal indicative of the run error and particular testing subroutine in which it occurred is sent to the system.

Abstract: An apparatus and method for transmitting information between dual redundant components comprises two information sources each of which is coupled to two transmitters, the outputs of which are coupled to four signal paths for transmission to two independent voters. Each of the voters compares predetermined pairs of the signals on the four signal paths and provides a preferred one of the signals to a corresponding receiver based on the results of the pair comparisons.