Abstract: A semiconductor memory device includes: a master chip suitable for generating a plurality of first control signals and a second control signal based on a read command; and a plurality of slave chips each suitable for latching data read from a plurality of memory cells included in a corresponding slave chip and transmitting the latched data to the master chip based on a correspond control signal of the first control signals, wherein the master chip latches the data transmitted from the slave chips based on the first control signals and outputs the data latched in the master chip based on the second control signal.

Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including a memory, a capture register, a writing unit, and a control unit. The memory includes a plurality of memory bit cells. The capture register stores data read out from a memory bit cell selected out of the plurality of memory bit cells. The writing unit writes relevant data according to the data stored in the capture register to the memory bit cell. The control unit reads the relevant data from the written memory bit cell, compares the relevant data according to the data stored in the capture register and the read-out relevant data, controls the capture register such that a comparison result is stored by overwriting a result as a self-test result about the written memory bit cell, and controls the writing unit such that the original data according to the read-out relevant data is rewritten to the selected memory bit cell.

Abstract: A method of switching a memristive device applies a current ramp of a selected polarity to the memristive device. The resistance of the device during the current ramp is monitored. When the resistance of the memristive device reaches the target value, the current ramp is removed.

Abstract: A simple, effective and economical method to improved the yield of CMOS devices using contact etching stopper liner, including, single neutral stressed liner, single stressed liner and dual stress liner (DSL), technology is provided. In order to improve the chip yield, the present invention provides a method in which a sputter etching process is employed to smooth/flatten (i.e., thin) the top surface of the contact etch stopper liners. When DSL technology is used, the inventive sputter etching process is used to reduce the complexity caused by DSL boundaries to smooth/flatten top surface of the DSL, which results in significant yield increase. The present invention also provides a semiconductor structure including at least one etched liner.

Abstract: The present disclosure includes a three dimensional (3D) integrated device comprising a first die having a first supply line and a second die having a second supply line, a power header, and voltage selection logic. The power header is connected to the first die and the second die and configured to generate a first voltage on a first voltage line and a second voltage on a second voltage line. The voltage selection logic is connected to the first supply line and the second supply line and configured to select between the first voltage line and the second voltage line for each of the first supply line and the second supply line.

Abstract: A method for repairing an oxide layer and a method for manufacturing a semiconductor structure applying the same are provided. The method for repairing an oxide layer comprises following steps. First, a carrier having a first area and a second area is provided, wherein a repairing oxide layer is formed on the second area. Then, the carrier is attached to a substrate with an oxide layer to be repaired formed thereon, wherein the carrier and the substrate are attached to each other through the repairing oxide layer and the oxide layer to be repaired. Thereafter, the oxide layer to be repaired is bonded with the repairing oxide layer.

Abstract: There is provided a non-volatile memory circuit including: plural storage element sections each including a zener zap device and a switch section that connects an anode of the zener zap device to an output terminal during data reading; and wherein cathodes of respective zener zap devices of the plural storage element sections are commonly connected so as to be connected to a power supply employed in the writing or to a power supply employed in the reading, wherein the output terminals of the plural storage element sections are commonly connected to an input terminal of a detector, an anode of each of the storage element sections being connected to a ground voltage during data writing, and wherein the switch section is switched ON during data reading so as to connect the anode of the storage element section through the output terminal to the input terminal of the detector.

Abstract: Described is an apparatus which comprises: a first memory unit having an input and an output, wherein the first memory unit operates on a first power supply which is operable to be turned off; a second memory unit having an input coupled to the output of the first memory unit, and an output, wherein the second memory unit operates on a second power supply which is always on; and a control logic coupled to the first and second memory units, the control logic to provide one or more control signals to each of the first and second memory units.

Abstract: A semiconductor memory device includes: a memory array including a plurality of memory cells; and a peripheral circuit configured to change a voltage level of a bit line connected to a program target cell according to a threshold voltage of the program target cell among the memory cells during a program operation.

Abstract: A method of determining a read voltage of a memory device includes performing a plurality of read operations with respective different read voltages on a first group of storage regions of the memory device using a first error correction rate, wherein the plurality of read operations are performed to distinguish between a pair of adjacent logic states of memory cells in the first group of storage regions, detecting a read voltage level, among the different read voltages, at which a minimum number of erroneous bits is generated in the at least one read operation, and determining a read voltage for a second group of storage regions to which a second error correction rate is applied, based on the detected read voltage level, wherein the first error correction rate is higher than the second error correction rate.

Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell array where memory cells are arranged in a row direction and a column direction in a matrix shape; word lines which select the memory cell in the row direction; bit lines which select the memory cells in the column direction; a sense amplifier circuit which determines values stored in the memory cells based on states of the bit line; and a charge/discharge circuit which is formed in a well where the memory cell array is arranged and which charges or discharges the bit lines.

Abstract: Memory devices, controllers, and electronic devices comprising memory devices are described. In one embodiment, a memory device comprises a volatile memory, a nonvolatile memory, and a controller comprising a memory buffer, and logic to transfer data between the nonvolatile memory and the volatile memory via the memory buffer in response to requests from an application, wherein data in the memory buffer is accessible to the application. Other embodiments are also disclosed and claimed.

Abstract: During a program operation of a fuse cell of a fuse circuit, all of a group of select transistors of a fuse cell are made conductive to program the fuse cell. During a test operation of a fuse cell of the fuse circuit, less than all of the group of select transistors are made conductive so that current less than a programming current flows through the fuse cell.

Abstract: A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver.

Abstract: Provided is a nonvolatile memory device using a resistance material and a method of driving the nonvolatile memory device. The nonvolatile memory device comprises a resistive memory cell which stores multiple bits; a sensing node; a clamping unit coupled between the resistive memory cell and the sensing node and provides a clamping bias to the resistive memory cell; a compensation unit which provides a compensation current to the sensing node; a sense amplifier coupled to the sensing node and senses a change in a level of the sensing node; and an encoder which codes an output value of the sense amplifier in response to a first clock signal. The clamping bias varies over time. The compensation current is constant during a read period.

Abstract: Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

Abstract: A method of operating a memory device includes programming a first data signal to a first memory cell, attempting to program a second data signal to the first memory cell in a state where the first memory cell is not erased, and marking the first memory cell as blank upon failing to program the second data signal to the first memory cell.

Abstract: Techniques, systems and circuitry for using One-Time Programmable (OTP) memories to function as a Multiple-Time Programmable (MTP) memory. The OTP-for-MTP memory can include at least one OTP data memory to store data, and at least one OTP CAM to store addresses and to search input address through valid entries of the OTP CAM to find a latest entry of the matched valid addresses. The OTP-for-MTP memory can also include a valid-bit memory to find a next available entry of the OTP data memory and OTP CAM. When programming the OTP-for-MTP memory, address and data can be both programmed into the next available entry of the OTP CAM and the OTP data memory, respectively. When reading the OTP-for-MTP memory, the input address can be used to compare with valid entries of the addresses stored in the OTP CAM so that the latest entry of the matched valid addresses can be output.

Abstract: According to one embodiment, a resistance-change memory includes a memory cell and a control circuit. The memory cell comprises first and second electrodes, and a variable resistance layer disposed between the first electrode and the second electrode. The control circuit applies a voltage between the first electrode and the second electrode to perform writing, erasing, and reading. During the writing, the control circuit applies a first voltage pulse between the first electrode and the second electrode, and then applies a second voltage pulse different in polarity from the first voltage pulse after applying the first voltage pulse.

Abstract: A non-volatile memory circuit is formed of a P-channel MOS transistor and includes a P-channel non-volatile memory element having a floating gate and a control gate capacitively coupled together. A resistor divider has a first resistor and a second resistor for dividing a voltage difference between a power supply voltage and a ground voltage. A divided voltage output of the resistor divider is connected to the control gate. First and second switches are connected in parallel to the respective first and second resistors. The first and second switches are controlled so that a voltage of the control gate is set to a voltage of the divided voltage output which maximizes an electric field between a pinch-off point and a drain point of the P-channel MOS transistor in a writing mode.