Abstract: The present invention is directed to a semiconductor chip comprising a high voltage device and a low voltage device disposed thereon. The chip may be formed in several different configurations. For example, the semiconductor chip may include a NPN bipolar transistor, PNP bipolar transistor, a diode, an N channel DMOS transistor and the like. the first doped well being configured as a base of the DMOS transistor, a P channel DMOS transistor and the like. These and other embodiments are described in further detail below.

Abstract: An imaging device includes a plurality of light-receiving elements arranged in a two-dimensional matrix shape. Each of the light-receiving elements includes a first electrode, a photoelectric conversion layer, and a second electrode. The photoelectric conversion layer has a laminated structure in which a first compound semiconductor layer having a first conductivity type and a second compound semiconductor layer having a second conductivity type that is a reverse conductivity type to the first conductivity type are laminated from a side of the first electrode. The second compound semiconductor layer has been removed in a region between the light-receiving elements. The first electrode and the first compound semiconductor layer are shared by the light-receiving elements. An impurity concentration of a first compound semiconductor layer near the first electrode is lower than that of a first compound semiconductor layer near the second compound semiconductor layer.

Abstract: A semiconductor module, including a laminated substrate that has an insulating plate, a circuit board disposed on a top surface of the insulating plate, and a heat dissipation plate disposed on a bottom surface of the insulating plate. The semiconductor module further has a semiconductor element disposed on a top surface of the circuit board, a metal wiring board disposed on a top surface of the semiconductor element, and a temperature sensor that detects a temperature of the semiconductor element, and that is disposed on a top surface of the metal wiring board. The metal wiring board includes a heat blocking part that blocks heat of the semiconductor element.

Abstract: In some embodiments, a semiconductor device includes a semiconductor die including a vertical transistor device having a source electrode, a drain electrode and a gate electrode, the semiconductor die having a first surface and a metallization structure located on the first surface. The metallization structure includes a first conductive layer on the first surface, a first insulating layer on the first conductive layer, a second conductive layer on the first insulating layer, a second insulating layer on the second conductive layer and a third conductive layer on the second insulting layer. The third conductive layer includes at least one source pad electrically coupled to the source electrode, at least one drain pad electrically coupled to the drain electrode and at least one gate pad electrically coupled to the gate electrode.

Abstract: A method for forming a light sensing device is provided. The method includes forming a light sensing region in a semiconductor substrate and forming a light shielding layer over the semiconductor substrate. The method also includes forming a dielectric layer over the light shielding layer and partially removing the light shielding layer and the dielectric layer to form a light shielding element and a dielectric element. A top width of the light shielding element is greater than a bottom width of the dielectric element. The light shielding element and the dielectric element surround a recess, and the recess is aligned with the light sensing region. The method further includes forming a filter element in the recess.

Abstract: Provided is a packaging structure, which includes a carrier and an electronic component, an antenna module and a connector disposed on the carrier, and a packaging layer encapsulating the electronic component and the connector. A portion of a surface of the connector is exposed from the packaging layer so as to facilitate the electrical connection with a motherboard of an electronic product. A method for fabricating the packaging structure is also provided.

Abstract: Examples for a two-step insert molding process to encapsulate a pre-molded lead frame (104, 304, 504, 704) are described herein. In some examples, a first circuit component (106, 306, 506) and a first portion of a trace array (110, 310, 510) of the pre-molded lead frame for an integrated circuit (1C) assembly are encapsulated by a first insert molding component (112, 312, 512a, 512b, 712). The trace array connects the first circuit component to a second circuit component (108, 308, 508) of the pre-molded lead frame. A second portion of the trace array is encapsulated by a second insert molding component (114, 314, 514, 714).

Abstract: A semiconductor apparatus includes a semiconductor substrate and a second electrode. Semiconductor substrate includes a device region and a peripheral region. An n? drift region and second electrode extend from device region to peripheral region. An n buffer layer and a p collector layer are provided also in peripheral region. Peripheral region is provided with an n type region. N type region is in contact with second electrode and n buffer layer. The turn-off loss of the semiconductor apparatus is reduced.

Abstract: A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25.

Abstract: A method may include thinning a silicon wafer to a particular thickness. The particular thickness may be based on a passband frequency spectrum of an adjustable optical filter. The method may also include covering a surface of the silicon wafer with an optical coating. The optical coating may filter an optical signal and may be based on the passband frequency spectrum. The method may additionally include depositing a plurality of thermal tuning components on the coated silicon wafer. The plurality of thermal tuning components may adjust a passband frequency range of the adjustable optical filter by adjusting a temperature of the coated silicon wafer. The passband frequency range may be within the passband frequency spectrum. The method may include dividing the coated silicon wafer into a plurality of silicon wafer dies. Each silicon wafer die may include multiple thermal tuning components and may be the adjustable optical filter.

Abstract: A power module substrate includes an insulating substrate and a metal plate. The metal plate is joined to the insulating substrate with a brazing material in between. As to surface roughness of a lateral surface of the metal plate in a thickness direction, the surface roughness of at least a corner part farthest from a center of the metal plate in plan view is larger than the surface roughness of plane parts sandwiching the corner part.

Abstract: A high-frequency transistor includes a source electrode, a drain electrode, a gate electrode, and a gate drive line that applies a voltage to the gate electrode. An impedance adjustment circuit is connected between the gate electrode and the gate drive line. A characteristic impedance of the gate electrode is Z1, when a connecting point between the impedance adjustment circuit and the gate electrode is viewed from the impedance adjustment circuit. A characteristic impedance of the gate drive line is Z2, when a connecting point between the impedance adjustment circuit and the gate drive line is viewed from the impedance adjustment circuit. X that denotes a characteristic impedance of the impedance adjustment circuit is a value between Z1 and Z2.

Abstract: A semiconductor device includes circuit substrates 3 and 9 including circuit pattern layers 3c/9b, a semiconductor element 5 mounted to the circuit pattern layer 3c, a connecting pin 7 connecting the semiconductor element 5 to the circuit pattern layer 9b, a pin-shaped terminal 17 connected to the circuit pattern layer 9b, a sealing member 2 sealing the circuit substrates 3 and 9, the semiconductor element 5, and the connecting pin 7, and an external terminal 27 including a flat plate portion 27s and an extending portion 27t bent from the flat plate portion 27s and extends away from the circuit substrate 9, in which the flat plate portion 27s is connected to the pin-shaped terminal 17 and arranged in parallel with the circuit pattern layer 9b, and the extending portion 27t is provided in a range of a width in a transverse direction of the sealing member 2.

Abstract: A packaged semiconductor device including an integrated passive device-containing package component disposed between a power module and an integrated circuit-containing package and a method of forming the same are disclosed. In an embodiment, a device includes a first package component including a first integrated circuit die; a first encapsulant at least partially surrounding the first integrated circuit die; and a redistribution structure on the first encapsulant and coupled to the first integrated circuit die; a second package component bonded to the first package component, the second package component including an integrated passive device; and a second encapsulant at least partially surrounding the integrated passive device; and a power module attached to the first package component through the second package component.

Abstract: Semiconductor devices include a substrate layer and a semiconductor layer formed over the substrate layer. A dielectric layer fills a gap between the semiconductor layer and the substrate layer, on end faces of the semiconductor layer, and on a top surface of the semiconductor layer.

Abstract: A semiconductor device includes first group active fins and a first diffusion prevention pattern. The first group active fins are spaced apart from each other in a second direction, and each of the first group active fins extends in a first direction different from the second direction on a first region of a substrate including the first region and a second region. The first diffusion prevention pattern extends on the first region of the substrate in the second direction through the first group active fins. The first group active fins include first and second active fins. The first diffusion prevention pattern extends through a central portion of the first active fin in the first direction to divide the first active fin, and extends through and contacts an end of the second active fin in the first direction.

Abstract: An electronic circuit is disclosed. The electronic circuit includes: a first transistor device integrated in an inner region of a first semiconductor body; and a first drive circuit integrated in a first drive circuit region of the semiconductor body. The first drive circuit is configured to be connected to a level shifter and to drive a second transistor device. The first drive circuit region is located in an edge region surrounding the inner region of the semiconductor body.

Abstract: The present disclosure provides a quantum dot and a manufacturing method for the same, and a luminescent material, a light-emitting element and a display device applying the quantum dot. The quantum dot includes a nano-crystal and a ligand. The nano-crystal is at least one selected from the group consisting of a XII-XV group compound semiconductor nano-crystal, a XII-XVI group compound semiconductor nano-crystal, a XIII-XV group compound semiconductor nano-crystal and a XIII-XVI group compound semiconductor nano-crystal. The ligand is disposed on a surface of the nano-crystal. The ligand contains 15%-70% of a fatty acid compound, 1%-35% of a phosphine compound, >0%-55% of a thiol compound, and 0%-10% of another ligand substance.

Abstract: A heat sink board according to an embodiment of the present invention includes a heat sink layer, an insulated layer formed on the heat sink layer, and a metal layer formed on the insulated layer, wherein both end parts of the heat sink layer and both end parts of the insulated layer are respectively projected further than the both end parts of the metal layer.

Abstract: A method includes receiving a structure having a dielectric layer over a conductive feature; etching a hole through the dielectric layer and exposing the conductive feature; depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature; depositing a second metal over the first metal; and annealing the structure including the first and the second metals.