Abstract: Embodiments of a three-dimensional silicon structure for integrated circuits and cooling thereof are described. In one aspect, a device includes a silicon substrate having a first primary side and a second primary side opposite the first primary side. The first primary side includes a circuit structure disposed thereon. The second primary side includes a plurality of fins monolithically formed thereon.

Abstract: A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.

Abstract: A semiconductor device includes a substrate, a two-dimensional (2D) material layer formed on the substrate and having a first region and a second region adjacent to the first region, and a source electrode and a drain electrode provided to be respectively in contact with the first region and the second region of the 2D material layer, the second region of the 2D material layer including an oxygen adsorption material layer in which oxygen is adsorbed on a surface of the second region.

Abstract: One embodiment of the present invention is a semiconductor device at least including an oxide semiconductor film, a gate insulating film in contact with the oxide semiconductor film, and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film therebetween. The oxide semiconductor film has a spin density lower than 9.3×1016 spins/cm3 and a carrier density lower than 1×1015/cm3. The spin density is calculated from a peak of a signal detected at a g value (g) of around 1.93 by electron spin resonance spectroscopy. The oxide semiconductor film is formed by a sputtering method while bias power is supplied to the substrate side and self-bias voltage is controlled, and then subjected to heat treatment.

Abstract: An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises: a thin film transistor (TFT 10) provided on a base substrate (01), a first passivation layer (200) provided on the thin film transistor (TFT 10), and a transparent electrode layer (300) provided on a surface of the first passivation layer (200). The first passivation layer (300) includes: a first sub-thin film layer (210), and a second sub-thin film layer (211) which is provided on a surface of the first sub-thin film layer (210) and in contact with the transparent electrode layer (300); and a film density of the second sub-thin film layer (211) is greater than that of the first sub-thin film layer (210).

Abstract: A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a first surface and a second surface. The thermal conductivity layer is attached to the first surface of the chip. The thermal conductivity layer provides a path through which heat generated from the chip is dissipated to the ambient. A substrate is attached to the second surface of the chip. A molding compound is formed above the substrate to encapsulate the chip and the thermal conductivity layer.

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnects extending in a first direction, a plurality of second interconnects extending in a second direction, a plurality of stacked films respectively provided between the first interconnects and the second interconnects, each of the plurality of stacked films including a variable resistance film, a first inter-layer insulating film provided in a first region between the stacked films, and a second inter-layer insulating film provided in a second region having a wider width than the first region. The second inter-layer insulating film includes a plurality of protrusions configured to support one portion of the plurality of second interconnects on the second region. A protruding length of the protrusions is less than a stacking height of the stacked films.

Abstract: An array substrate and a display device are provided. The array substrate includes a plurality of data lines; a plurality of gate lines; and a plurality of sub-pixel units defined by the gate lines and the data lines intersecting each other. The sub-pixel unit includes a first pixel electrode and a second pixel electrode respectively disposed on two sides of the gate line and a common electrode disposed between the first pixel electrode and the second pixel electrode. At least a first compensation electrode is connected to at least a side of the common electrode, at least a part of projection of it on a plane having the first pixel electrode overlaps the first pixel electrode; and/or at least a second compensation electrode is connected to a side of the first pixel electrode, and at least a part of projection of it on a plane having the common electrode overlaps the common electrode. The display device can have a wide viewing angle.

Abstract: The disclosed technology generally relates to magnetic devices, and more particularly to spin torque devices. In one aspect, a spin torque majority gate device includes a free ferromagnetic layer, a spin mixing layer formed above the free ferromagnetic layer, a non-magnetic tunnelling layer formed above the spin mixing layer, and a plurality of input elements formed above the non-magnetic tunnelling layer, where each input element has a fixed ferromagnetic layer.

Abstract: A semiconductor device having semiconductor device having a multi-height structure is provided. The semiconductor device having a multi-height structure includes a semiconductor substrate. A first structure and a second structure are respectively disposed on the semiconductor substrate and connected to each other. The second structure includes a limiting layer disposed on the upper surface of the semiconductor substrate, a first polysilicon layer disposed conformally on the limiting layer and the semiconductor substrate, and a second polysilicon layer disposed conformally on the first polysilicon layer. A ridge of the second polysilicon layer is disposed near an edge of the second structure beside the first structure, vertically aligned with the limiting layer and defined as a limiting block.

Abstract: A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile.

Abstract: Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer is formed on a substrate and includes a first semiconductor device, the first semiconductor device including a first electrode structure. The second device layer is formed on the first device layer and includes a second semiconductor device, the second semiconductor device including a second electrode structure. The first inter-level connection structure includes one or more first conductive materials and is configured to electrically connect to the first electrode structure and the second electrode structure.

Abstract: A method and an apparatus for cooling a semiconductor device. The method comprises the steps of contacting a surface of the semiconductor device with respective end portions of an array of contact elements thermally coupled to a cooling fluid, and disposing a flexible, heat conductive sheet between the respective end portions of the contact elements and the surface of the semiconductor device for transferring heat generated in the semiconductor device to the cooling fluid via the sheet and the contact elements.

Abstract: A semiconductor device includes a transistor including an insulating film, an oxide semiconductor film, a gate electrode overlapping with the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film; a capacitor including a first light-transmitting conductive film over the insulating film, a dielectric film over the first light-transmitting conductive film, and a second light-transmitting conductive film over the dielectric film; an oxide insulating film over the pair of electrodes of the transistor; and a nitride insulating film over the oxide insulating film. The dielectric film is the nitride insulating film, the oxide insulating film has a first opening over one of the pair of electrodes, the nitride insulating film has a second opening over the one of the pair of electrodes, and the second opening is on an inner side than the first opening.

Abstract: An object of the invention is to provide a semiconductor device having less cracking or peeling and a method of manufacturing the same. A fuse portion of a semiconductor device has bit lines electrically coupled to a SRAM memory cell. The bit lines are covered by an interlayer insulating film. As the interlayer insulating film, a boron-doped BPTEOS film is formed. The bit lines have thereabove a fuse. The fuse and the bit lines are electrically coupled to each other via contact plugs. The interlayer insulating film that covers the bit lines therewith is separated from the contact plugs.

Abstract: Methods for manufacturing semiconductor light-emitting devices and semiconductor light-emitting devices having a high radiating performance and can include a metallic laminate substrate, a semiconductor light-emitting chip and a transparent resin. The metallic laminate substrate can include a cavity so as to be able to accurately mount the light-emitting chip, and also can structures to efficiently radiate heat generated from the light-emitting chip. The transparent resin to encapsulate the semiconductor light-emitting chip in the cavity can include various wavelength converting materials. Additionally, the light-emitting devices can be manufactured in manufacturing processes similar to conventional light-emitting devices.

Abstract: A layout structure is provided. The layout structure includes a substrate, a gate conductive layer, a first doped region having a first conductivity, a second doped region having the first conductivity, and a third doped region having a second conductivity. The gate conductive layer is formed on the substrate. The first doped region the second doped region are formed in the substrate and located at two sides of the gate conductive layer. The third doped region is formed in the substrate and adjacent to the second doped region. The third doped region and the second doped region form a diode. The gate conductive layer, the first doped region, and the third doped region are connected to ground, and the second doped region is connected to an input/output pad.

Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate, and the method comprises steps of: 1, forming a gate (3) and a first heavily doped transparent conducting thin film layer (2) on a substrate (1); 2, deposing a gate isolation layer (4); 3, forming an island shaped oxide semiconductor layer (5); 4, forming an island shaped photoresistor layer (6); 5, forming a source/a drain (8), and a second, a third heavily doped transparent conducting thin film layer (7, 9), and the source/the drain (8) contact the two side parts (53) of the island shaped oxide semiconductor layer (5) via the second heavily doped transparent conducting thin film layer (7) to establish electrical connections; 6, deposing and patterning a protecting layer (10); 7, deposing and patterning a pixel electrode layer (11) which contacts the source/the drain (8) via the third heavily doped transparent conducting thin film layer (9) to establish electrical connections; 8, implementing anneal process.

Abstract: A method of reducing line bending and surface roughness of a substrate with pillars includes forming a treated surface by treating a pillar-containing substrate with a radical. The radical may be silicon-based, nitrogen-based or oxygen-based. The method may include forming a dielectric film over the treated surface by reacting an organosilicon precursor and an oxygen precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. A method of reducing line bending and surface roughness of a substrate with pillars includes forming a dielectric film over a pillar-containing substrate by reacting an organosilicon precursor, an oxygen precursor, and a radical precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. The radical precursor may be selected from the group consisting of nitrogen-based radical precursor, oxygen-based radical precursor, and silicon-based radical precursor.

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm?2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.