Patents Examined by Alonzo Chambliss
  • Patent number: 11915999
    Abstract: A semiconductor device includes: a carrier including an electronic circuit; a plurality of semiconductor chip packages mounted on the carrier, each of the chip packages including an encapsulation encapsulating the semiconductor chip, a plurality of contact structures electrically connecting the semiconductor chip with the electronic circuit, and at least one cooling structure protruding from the encapsulation; and a cooling element thermally conductively connected to at least one cooling structure of each of at least two of the plurality of semiconductor chip packages.
    Type: Grant
    Filed: January 31, 2023
    Date of Patent: February 27, 2024
    Assignee: Infineon Technologies AG
    Inventors: Tomasz Naeve, Ralf Otremba, Thorsten Scharf, Markus Dinkel, Martin Gruber, Elvir Kahrimanovic
  • Patent number: 11908771
    Abstract: A molded semiconductor package includes: a semiconductor die; a substrate attached to a first side of the semiconductor die; a plurality of leads electrically connected to a pad at a second side of the semiconductor die opposite the first side; a heat sink clip thermally coupled to the pad; and a molding compound encapsulating the semiconductor die, part of the leads, part of the heat sink clip, and at least part of the substrate. The molding compound has a first main side, a second main side opposite the first main side and at which the substrate is disposed, and an edge extending between the first main side and the second main side. The leads protrude from opposing first and second faces of the edge of the molding compound. The heat sink clip protrudes from opposing third and fourth faces of the edge of the molding compound.
    Type: Grant
    Filed: November 12, 2021
    Date of Patent: February 20, 2024
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Angel Enverga, Chii Shang Hong, Chee Ming Lam, Sanjay Kumar Murugan, Subaramaniym Senivasan
  • Patent number: 11901268
    Abstract: An external terminal electrode is attached to a frame, and the frame contains a first resin, and has a first adhered surface. A heat sink plate supports the frame, has an unmounted region where a power semiconductor element is to be mounted within the frame in plan view, is made of metal, and has a second adhered surface. An adhesive layer contains a second resin different from the first resin, and adheres the first adhered surface of the frame and the second adhered surface of the heat sink plate to each other. One of the first and second adhered surfaces includes a flat portion and a protruding portion. The protruding portion protrudes from the flat portion and opposes the other one of the first adhered surface and the second adhered surface with the adhesive layer therebetween.
    Type: Grant
    Filed: November 19, 2021
    Date of Patent: February 13, 2024
    Assignees: NGK Electronics Devices, Inc., NGK INSULATORS, LTD.
    Inventors: Yoshio Tsukiyama, Teppei Yamaguchi
  • Patent number: 11901273
    Abstract: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: February 13, 2024
    Assignee: Infineon Technologies AG
    Inventors: Ivan Nikitin, Peter Luniewski
  • Patent number: 11894366
    Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: February 6, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Jonghae Kim, Milind Shah, Periannan Chidambaram
  • Patent number: 11894287
    Abstract: Provided are a package structure and a method of forming the same. The package structure includes a first die, a second die group, an interposer, an underfill layer, a thermal interface material (TIM), and an adhesive pattern. The first die and the second die group are disposed side by side on the interposer. The underfill layer is disposed between the first die and the second die group. The adhesive pattern at least overlay the underfill layer between the first die and the second die group. The TIM has a bottom surface being in direct contact with the first die, the second die group, and the adhesive pattern. The adhesive pattern separates the underfill layer from the TIM.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: February 6, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Chin-Fu Kao, Li-Hui Cheng, Szu-Wei Lu, Chih-Chien Pan
  • Patent number: 11894290
    Abstract: A power device for surface mounting has a leadframe including a die-attach support and at least one first lead and one second lead. A die, of semiconductor material, is bonded to the die-attach support, and a package, of insulating material and parallelepipedal shape, surrounds the die and at least in part the die-attach support and has a package height. The first and second leads have outer portions extending outside the package, from two opposite lateral surfaces of the package. The outer portions of the leads have lead heights greater than the package height, extend throughout the height of the package, and have respective portions projecting from the first base.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: February 6, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Cristiano Gianluca Stella, Fabio Vito Coppone, Francesco Salamone
  • Patent number: 11887952
    Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu
  • Patent number: 11888055
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: January 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Patent number: 11876028
    Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: January 16, 2024
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
  • Patent number: 11870014
    Abstract: The present disclosure provides an encapsulated fluorescent adhesive layer, a method for manufacturing the same, and a quantum dot backlight. The quantum dot backlight includes a substrate, a light emitting chip, and the encapsulated fluorescent adhesive layer. The encapsulated fluorescent adhesive layer is used for heat transfer and heat dissipation.
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: January 9, 2024
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hongquan Wei
  • Patent number: 11868047
    Abstract: A method of manufacturing a semiconductor device includes applying a polymer mixture over a substrate, exposing and developing at least a portion of the polymer mixture to form a developed dielectric, and curing the developed dielectric to form a dielectric layer. The polymer mixture includes a polymer precursor, a photosensitizer, and a solvent. The polymer precursor may be a polyamic acid ester.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sih-Hao Liao, Yu-Hsiang Hu, Hung-Jui Kuo, Chen-Hua Yu
  • Patent number: 11862538
    Abstract: In some examples a semiconductor chip package includes a conductive terminal. In addition, the semiconductor chip package includes a die pad including a top side and a recess extending into the top side. The die pad is downset relative to the conductive terminal. Further, the semiconductor ship package includes a semiconductor die positioned within the recess, wherein the semiconductor die has an outer perimeter, and a solder fillet engaged within the recess and with the outer perimeter of the semiconductor die. Still further, the semiconductor chip package includes a wire bond coupled to the semiconductor die and the conductive terminal, and a mold compound covering the conductive terminal, the wire bond, the die pad, and the semiconductor die.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chung-Hao Lin, Hung-Yu Chou, Bo-Hsun Pan, Dong-Ren Peng, Pi-Chiang Huang, Yuh-Harng Chien
  • Patent number: 11864317
    Abstract: A method of manufacturing a circuit substrate includes forming, in an insulating substrate and circuit patterns that are provided on a first surface and a second surface of the insulating substrate, a through-hole penetrating the insulating substrate and the circuit patterns, where the circuit patterns contain Cu as a main component. The method includes filling, in the through-hole, an electrically conductive paste that is a melting-point shift electrically conductive paste including Sn—Bi solder powder, Cu powder, and resin, and forming a protrusion obtained by causing the electrically conductive paste to protrude from the through-hole. The method further includes performing pressure treatment on the protrusion near the through-hole; and performing heat treatment on the insulating substrate whose protrusion is subjected to the pressure treatment and causing the circuit patterns and the electrically conductive paste to be electrically connected with each other.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: January 2, 2024
    Assignee: NICHIA CORPORATION
    Inventors: Masaaki Katsumata, Koji Taguchi, Norifumi Sasaoka, Yosuke Noda
  • Patent number: 11862736
    Abstract: Multi-dimensional photonic integrated circuits are provided, including a substrate having a first side and a second side, a multi-dimensional package having multi-dimensional planes, and one or more optical components connected to the first side and the second side of the substrate and on the multi-dimensional planes of the multi-dimensional package. The multi-dimensional planes include one or more horizontal sides and one or more vertical sides. One or more of the optical components are mounted on at least one of the horizontal sides of the multi-dimensional package and one or more of the optical components are mounted on at least one of the vertical sides of the multi-dimensional package. Hybrid systems of conventional multi-dimensional integrated circuits and multi-dimensional photonic integrated circuits also are provided.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: January 2, 2024
    Assignee: GBT Tokenize Corp.
    Inventors: Danny Rittman, Aliza Schnapp
  • Patent number: 11862541
    Abstract: A molded semiconductor package includes a mold compound, a plurality of leads each having a first end embedded in the mold compound and a second end protruding from a side face of the mold compound, and a semiconductor die embedded in the mold compound and electrically connected, within the mold compound, to the plurality of leads. The second end of each lead of the plurality of leads has a bottom surface facing in a same direction as a bottom main surface of the mold compound. Each lead of the plurality of leads has a negative standoff relative to the bottom main surface of the mold compound.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: January 2, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Stoek, Dirk Ahlers, Stefan Macheiner
  • Patent number: 11854949
    Abstract: The present invention provides a package structure and a method for manufacturing the same. The package structure includes at least two electrical elements, a second reconstruction layer, and a metal lead frame, wherein at least one of the electrical elements is a chip, at least one of the electrical elements has a first reconstruction layer, and the second reconstruction layer has a smaller pin pitch than that of the metal lead frame; the second reconstruction layer has a first surface and a second surface, a functional surface of the electrical element is disposed on and connected to the first surface, and at least one of the electrical elements is connected to the second reconstruction layer; and the second surface is disposed on and connected to the metal lead frame. A fan-out package structure is formed on the metal lead frame, which improves the heat dissipation capacity of the chip.
    Type: Grant
    Filed: November 20, 2021
    Date of Patent: December 26, 2023
    Assignee: JCET GROUP CO., LTD.
    Inventors: Yaojian Lin, Danfeng Yang, Shuo Liu, Chenye He
  • Patent number: 11854918
    Abstract: A semiconductor package includes a first die. The first die has a first side and a second side different from the first side and includes a first seal ring. The first seal ring includes a first portion at the first side and a second portion at the second side, and a width of the first portion is smaller than a width of the second portion.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen, Chih-Chia Hu
  • Patent number: 11848280
    Abstract: An assembly structure and a method for manufacturing the same are provided. The method for manufacturing the assembly structure includes providing a substrate defining an active region and a side rail surrounding the active region; and forming a frame structure on the side rail.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: December 19, 2023
    Assignee: ADVANCED SEMlCONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Yu-Ju Liao
  • Patent number: 11848409
    Abstract: A display device includes a substrate including a display area and a non-display area, a pixel located in the display area, a pad unit on one side of the non-display area, and a driver connected to the pixel. The pixel includes a first insulating layer, a first light emitting element on the first insulating layer, a second insulating layer on the first light emitting element and exposing one end portion and another end portion of the first light emitting element, a first contact electrode on the second insulating layer and connected to the one end portion of the first light emitting element, and a second contact electrode on the second insulating layer and connected to the other end portion of the first light emitting element. The pad unit includes a pad metal layer, a first pad insulating layer, a second pad insulating layer, and a pad electrode.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: December 19, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Yeong Kim, Mi Jin Park, Sang Ho Park, Tae Hoon Yang, Sung Jin Lee