Abstract: A self-snooping mechanism for enabling a processor being coupled to dedicated cache memory and a processor-system bus to snoop its own request issued on the processor-system bus. The processor-system bus enables communication between the processor and other bus agents such as a memory subsystem, I/O subsystem and/or other processors. The self-snooping mechanism is commenced upon determination that the request is based on a boundary condition so that initial internal cache lookup is bypassed to improve system efficiency.

Abstract: An apparatus and method, using an inter-processor lock to control access to inter-process relationship data structures in the memory of each processor in a multiprocessor system. The apparatus and method insure that each inter-process relationship is modified in the same sequence on each processor. The apparatus and method also insure that an inter-process relationship is maintained in a consistent state in the face of failure of any of the processors.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A general purpose, programmable media processor for processing and transmitting a media data stream of audio, video, radio, graphics, encryption, authentication, and networking information in real-time. The media processor incorporates an execution unit that maintains substantially peak data throughout of media data streams. The execution unit includes a dynamically partionable multi-precision arithmetic unit, programmable switch and programmable extended mathematical element. A high bandwidth external interface supplies media data streams at substantially peak rates to a general purpose register file and the multi-precision execution unit. A memory management unit, and instruction and data cache/buffers are also provided. High bandwidth memory controllers are linked in series to provide a memory channel to the general purpose, programmable media processor.

Abstract: A data processing system (10) includes a register bit structure (27) which can be hard-wired (37, 39) but is also selectively configureable for read/write operation.

Abstract: An apparatus and method for communicating information between a computer and a plurality of peripherals along a plurality of communication channels is disclosed. The computer and peripherals are connected in a succession of stages (cascaded), in a tree-like (hierarchical) communication network configuration. Peripherals in the network include an associated communication unit which is responsible for transmitting and/or receiving data communicated on a communication channel. The communication unit facilitates the transfer of data to, and the receipt of data from, the unit's parent, and also facilitates the transfer of data to, and the receipt of data from, any child units. In the invented method, each communication unit, in parallel, composes those individual messages received from child units into a single composite message and transmits the composite message to the communication unit's parent.

Abstract: An integrated circuit CPU is provided. The CPU has a program counter register; an instruction register; an instruction decoder connected directly to the instruction register; a register file responsive to control signals from the instruction decoder; an ALU operating upon data from the register file and generating results responsive to the control signals; and a result register that holds results while the results are written back to the register file. The CPU has only three pipelined stages of operation. The three stages comprise fetching an instruction from the memory subsystem into the instruction register; executing an instruction in the instruction register; and writing back results in the result register to the register file. Operating speeds are comparable to CPUs with a greater number of stages.

Abstract: The present invention permits mounting and optimization of a hierarchically necessary number of units corresponding to the scale of input/output subsystems. An input/output subsystem is organized by dividing it into a basic portion including power units and an expanded portion including one or more input/output units. Each of the input/output subsystems has a plurality of built-in magnetic disk modules. The enclosure of a subsystem are composed of a basic enclosure mounting thereon power units and a prescribed number of input/output units forming a basic portion, and an expanded enclosure mounting thereon remaining input/output units other than those mounted on the basic enclosure. The power unit automatically recognizes the mounting status of input/output units, and ensures a necessary power supply capacity.

Abstract: A system and method for rationalizing physician data in which source data is collected from source computers located at, for example, physicians' offices, hospitals, testing laboratories and pharmacies. Source data is expected to be in diverse formats and syntax, according to the particular hardware/software/operating system configuration of the source computer. Source data is converted to a common format, advantageously ASCII text, and is parsed and binned into a standard data element "layout." Source data is then cross-referenced and cleaned against standard data resources such as Medicare UPIN tables and AMA ICD9 tables. In this way, analogous data elements acquire a common alphanumeric syntax. Keying errors may also be corrected and missing information may be supplied. Source data is then ready to be accumulated into a standard database of universal format.

Abstract: A method and a processing apparatus for use in a parallel computer realizing a coordinate scheduling which does not degrade a throughput performance of a system. According to this invention, if a parallel process in execution gets into a parallel synchronization waiting state, the parallel process is deactivated so that allocation of the parallel process is inhibited, a process of another executable job is allocated, instead. If a setting condition is satisfied during the execution of another job, an interruption signal for a process in execution is generated to activate the parallel process in the parallel synchronization waiting state, thereby resuming allocation of this parallel process. This invention may be applied to a parallel computer system of a distributed main storage MIMD type which implements plural tasks in parallel by plural PEs.

Abstract: A digital microelectronic replacement package includes at least one buffer die in combination with a programmable device or memory. The buffer die performs the functions of impedance-matching, delay-matching, and voltage-matching, while the programmable device or memory can be used to emulate the logic and/or storage functions of the original digital microelectronic circuit; the package of the invention can be used as a direct replacement for a digital microelectronic circuit without the requirement that the original circuit board be redesigned to accommodate modern voltage, impedance, and delay specifications associated with the programmable device or memory.

Abstract: A computer peripheral interface solves the problem of the interrupt-line mismatch between the PCI and ISA bus architectures without requiring additional interrupt lines between ISA devices and the computer. To accomplish this, a PCI-ISA bridge is provided that responds to ISA interrupts by generating a predetermined software interrupt instruction over the PCI bus. The peripheral interface includes a software-interrupt register and associated circuitry for accepting this software interrupt instruction and generating a corresponding simulated hardware interrupt. To solve problems associated with allowing two like-addressed devices to share a single bus, the computer peripheral interface uses a unique subtractive decoding scheme that allows the processor to selectively access either an internal floppy disk drive controller or a like-addressed peripheral floppy disk drive controller on the shared PCI bus.

Abstract: A method in accordance with the invention involves the normalization of a C language-type data structure received by a process in a distributed computing environment (DCE) to ensure that padding bits are consistently used. The method steps may advantageously be performed by a client process prior to and subsequent to a remote procedure call (RPC) to ensure that the padding bits are not undesirably changed as a result of the RPC. The method steps can also be performed by a server process to ensure that the structures it receives in RPCs are consistent in their use of padding bits. Normalization of the data structure permits a memcmp( ) or similar comparison function to be used to compare data structures without the risk that dissimilar padding bits will result in a false negative from the comparison.

Abstract: State machines having a hierarchical arrangement of machines as between a parent state machine 10 and sibling state machines 11, 12, and 14. The parent state machine 10 generates a plurality of outputs constituting its output state as based upon its input state defined by inputs N and its internal state. Part of the input state is defined by a set of inputs 15 which include asynchronous signals such as reset and interrupts. The parent state machine 10 defines or partially defines input states as applied to the respective sibling state machines 11, 12, and 14 by producing a series of output states in response to input states as applied thereto and independent upon an existing internal state. This system enables machine design time to be reliably shortened by virtue of easier validation of tasks assigned to the sibling machines.

Abstract: A computer processor that performs operations in a logarithmic number system (LNS) domain includes a log converter (20) which generates log signals, a data pipeline (22), a plurality of processing elements (231a-f) coupled to respective stages (24a-d) of the data pipeline, an inverse-log converter (28), and a programmable accumulator (232) that performs various summing operations to produce an output signal. An instruction, selected from a set of instructions, is decoded by a control unit (234) to configure the computer processor to perform operations on one or more data streams. Mathematical operations that can be performed by the processor include matrix multiplication, matrix-inversion, fast Fourier transforms (FFT), auto-correlation, cross-correlation, discrete cosine transforms (DCT), polynomial equations, and difference equations in general, such as those used to approximate infinite impulse response (IIR) and finite impulse response (FIR) filters.

Abstract: A short message server (SMS) is provided with memory for storing short messages, and a SMS gateway/interworking (processing) block. The SMS accepts all properly formatted incoming messages, and queries an HLR database for destination information as well as to determine whether the destination of each incoming message is valid and authorized. If the destination is either not valid or not authorized, the SMS sends an error message to the originator, and effectively deletes the message from its memory. Where the destination is valid and authorized, the message is forwarded towards its destination. The SMS specifically does not include a subscriber database, and instead relies on the communication with the HLR and its subscriber database to provide the necessary information. Communication between the SMS and the HLR is preferably via the GSM MAP (mobile application part) protocol.

Abstract: First and second banks of control stores are used to store microinstructions. Each bank contains three control stores: A horizontal control store, a vertical control store, and a jump control store. The horizontal control store contains the rank four microcode; the vertical control store contains the rank three microcode; and the jump control store contains the same microcode as the vertical control store but is used on conditional jump microoperations. This allows simultaneous accessing of different microinstructions using a single address incrementer. The control store banks are accessed in an overlapping manner so that upon each clock cycle one bank is loading the rank 3 and rank 4 registers. The sequencer according to the present invention includes a return address stack for returning from subroutine calls and trap routines.

Abstract: A computer having a riser card with a riser card interface that connects to an industry standard system board and has slots for expansion cards is provided with support circuitry that enables the computer system to perform personalized functions not provided for by the industry standard system board, including security functions. The placing of the support circuitry on the riser card allows the use of an industry standard system board and the personalization of the system to perform different IBM PS/2 functions depending on the installed riser card, in conjunction with Micro Channel and PCI bus architecture.

Abstract: A method and system in a data processing system are disclosed for efficiently managing an indication of a status of each of a plurality of registers included with the data processing system. An array is established having multiple entry fields for storing multiple entries. Each of the multiple entry fields is associated with a different one of the plurality of registers. A status of each of the plurality of registers is determined. A plurality of partitions are established within the array. Each of the partitions are concurrently accessible by the data processing system. A plurality of the multiple entry fields are associated with one of the plurality partitions. An entry is stored in each of the multiple entry field. The entry includes the status of each of the plurality of registers. Each entry is associated with one of the partitions so that a plurality of the multiple entries may be concurrently accessed.

Abstract: A data processing method which makes it unnecessary to run a user application program describing detailed conditions under which data on a device having a memory are acquired each time a system is started. A main controller forms a text format file as a data acquisition condition for a PLC from which data is to be acquired so that the data acquisition condition is associated with a label name, the data acquisition condition including a supervisory interval for supervising the status of the PLC and the operation status of the PLC for setting a trigger condition for starting data acquisition. When receiving the label name and the corresponding data acquisition condition from the main controller, a subcontroller develops and stores is the received data acquisition condition in a memory so that the data acquisition condition is associated with the label name.