Patents Examined by Alva C. Powell
  • Patent number: 6245191
    Abstract: Wet etch methods of anisotropically etching a substantially vertical etched step in a film. Methods of forming a substantially vertical etched step include depositing an etching solution droplet upon the surface of the film to be etched and monitoring at least one characteristic parameter of the etching solution droplet. Control of the etching solution droplet is carried out corresponding to monitored parameters of the etching solution droplet. Control is carried out through infusion and effusion of the etching solution droplet in order to replenish the chemical reactants in the etching solution droplet. Replenishing the etching solution droplet, while keeping the droplet of a uniform size, maintains a uniform etching chemistry as the etching solution droplet would otherwise constantly change in its chemistry as it etches material from the surface being etched.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: June 12, 2001
    Assignee: Micron Technology, Inc.
    Inventors: Garo J. Derderian, Gurtej S. Sandhu
  • Patent number: 6239032
    Abstract: A silicon nitride film is formed on a base layer having a silicon oxide film and a trench, in such a manner that the trench of the base layer is filled with the silicon nitride film. Subsequently, the silicon nitride film is selectively polished with reference to the silicon oxide film, with the silicon oxide film used as a stopper. The silicon nitride film is polished in a chemical mechanical polishing process that uses slurry containing a phosphoric acid and silica whose particle diameter is less than 10 nm, or slurry containing a phosphoric acid derivative and silica whose particle diameter is less than 10 nm. As a result of this selective polishing, the silicon nitride film selectively remains inside the trench.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: May 29, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenro Nakamura, Hiroyuki Yano
  • Patent number: 6235120
    Abstract: Improved semiconductor processing chamber parts are provided. An improved part is made of an underlying part having both an intermediate coating and a surface layer applied thereto. The intermediate coating includes a plurality of layers each having a CTE intermediate the CTE of the underlying part and the CTE of the surface layer. The intermediate coating reduces the stress between any two layers, allowing use of underlying parts and surface layers having dissimilar CTEs. The universe of acceptable materials for use within a semiconductor processing chamber is expanded, as fewer selection criteria exist for a given layer.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: May 22, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Won Bang, Chen-An Chen
  • Patent number: 6228280
    Abstract: A method for detecting the endpoint for removal of a target film overlying a stopping film by chemical-mechanical polishing using a slurry, by removing the target film with a polishing process that generates a chemical reaction product (for example ammonia when polishing a wafer with a nitride film in a slurry containing KOH) in the slurry, adding to the slurry a reagent which produces a characteristic result upon reacting with the chemical reaction product, and monitoring the slurry for the characteristic result as the target film is removed.
    Type: Grant
    Filed: May 6, 1998
    Date of Patent: May 8, 2001
    Assignee: International Business Machines Corporation
    Inventors: Leping Li, James Albert Gilhooly, Clifford Owen Morgan, III, Cong Wei
  • Patent number: 6225138
    Abstract: This patent describes a method of manufacturing a pulsed magnetic field ink jet print head wherein an array of nozzles are formed on a substrate utilising planar monolithic deposition, lithographic and etching processes. Multiple ink jet heads are formed simultaneously on a single planar substrate such as a silicon wafer. The print heads can be formed utilising standard VLSI/ULSI processing and can include integrated drive electronics formed on the same substrate. The drive electronics preferably being of a CMOS type. In the final construction, ink can be ejected from the substrate substantially normal to the substrate plane.
    Type: Grant
    Filed: July 10, 1998
    Date of Patent: May 1, 2001
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 6221204
    Abstract: A stackable processing chamber apparatus includes a processing chamber unit and a driving device for driving said transmitting shaft to rotate. The processing chamber unit includes a body defining a chamber. The processing chamber unit is provided with an evacuating pipeline passing through the processing chamber unit and communicating with the chamber, a draining pipeline passing through the processing chamber unit and communicating with the chamber, a chuck rotatably mounted within the processing chamber unit, a transmitting mechanism for driving the chuck to rotate, and a transmitting shaft passing through the body and driving the transmitting mechanism.
    Type: Grant
    Filed: January 27, 2000
    Date of Patent: April 24, 2001
    Inventor: Yu-tsai Liu
  • Patent number: 6214162
    Abstract: This invention relates to a plasma generating apparatus having a plasma generating electrode, and improves the controllability of the etching selectivity and the etching shape. In a plasma processing apparatus, an electrode is located in a processing chamber. A plasma generating RF power is supplied from a plasma generating RF power supply to the electrode. A to-be-processed object W is mounted on a lower electrode located in the processing chamber. RF powers having their phases adjusted to predetermined values are applied to the plasma generating electrode and the lower electrode. RF powers of a continuous wave or RF power pulse trains can be used as the RF powers.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: April 10, 2001
    Assignee: Tokyo Electron Limited
    Inventor: Chishio Koshimizu
  • Patent number: 6207007
    Abstract: A plasma processing system controls the electronegativity of a plasma produced by ionizing a process gas when processing a substrate by using the plasma. The relation between the pressure in a processing vessel (1) and the frequency of a RF power source (11′), and the electronegativity of the plasma produced by the agency of RF power is determined beforehand. A controller (18) adjusts the pressure in the processing vessel (1) and/or the frequency of the RF power source (11′) in a real-time control mode by a feedback control operation on the basis of a pressure measured by a pressure sensor (17) and a frequency measured by a frequency meter (15) to adjust the electronegativity of the plasma to an appropriate value. The electronegativity of the plasma can be determined through simulation using a one-dimensional RCT model of the plasma.
    Type: Grant
    Filed: March 25, 1999
    Date of Patent: March 27, 2001
    Assignees: Tokyo Electron Limited
    Inventors: Sumie Segawa, Toshiaki Makabe
  • Patent number: 6202589
    Abstract: An etch apparatus is presented including a grounding mechanism which maintains a low resistance electrical ground path between a plate electrode and a chamber despite temperature variations. The etch apparatus includes a chamber having a removable upper housing, a plate electrode positioned within the upper housing, and a grounding mechanism positioned between the plate electrode and the upper housing such that it contacts both the plate electrode and the upper housing. The grounding mechanism electrically couples the plate electrode to the upper housing. Several embodiments of the grounding mechanism include at least one sheet of metal folded to form two sections extending in an acute angle relative to one another. In two embodiments, the folded sheet of metal forms two sections meeting at a crease. Each of the two sections has an outer edge opposite the crease.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: March 20, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Stephanie A. Grahn, Donald L. Friede, Toby J. Winters
  • Patent number: 6200413
    Abstract: A system and method for polishing spherical shaped devices is disclosed. The system includes a carrier and an enclosure. The carrier has two projections so that when a device is placed between the projections, it contacts the carrier at two contact points. The enclosure matingly engages with the carrier so that it also contacts each device at two contact points. A movement system, such as a motor, provides relative movement between the carrier and the enclosure so that the four contact points polish each device. Also, the relative movement moves each device so that the device's entire outer surface is polished by the apparatus.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: March 13, 2001
    Assignee: Ball Semiconductor, Inc.
    Inventors: Roger Privitt, Akira Ishikawa, Takashi Kanatake
  • Patent number: 6197212
    Abstract: A process for the conditioning of dental cavities by etching in preparation for bonding restoration to enamel and dentin, comprising the steps: a) etching the dentin part of a dental cavity using an aqueous composition containing, as an active constituent, EDTA, in an effective amount, and b) etching the enamel part of said cavity using a conventional etching acid; and a kit for use in such process for conditioning.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: March 6, 2001
    Assignee: Peridoc AB
    Inventors: Sven Lindskog, Leif Blomlöf
  • Patent number: 6195229
    Abstract: A method of manufacturing a thin film merged magnetic head including an inductive write structure and a magnetoresistive sensor uses a patterned protection layer to protect a second shield/bottom pole layer in regions spaced from the pole tip of the inductive write structure. A window is provided in the protection layer. During manufacture, the configuration comprises a first shield layer, a magnetoresistive element, a second shield layer serving as a bottom pole, a protection layer, a protection window, a write gap, a top pole, and a pole tip structure. The use of a protection layer and window results in the formation of channels in the second shield layer adjacent to a pedestal that supports the inductive write structure. The channels prevent magnetic flux from extending toward the second shield layer beyond the width of the pole tip structure. This structure reduces side writing with a consequent improvement in off-track performance.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: February 27, 2001
    Assignee: Read-Rite Corporation
    Inventors: Yong Shen, Bertha Higa-Baral, Lien-Chang Wang
  • Patent number: 6190495
    Abstract: The magnetron plasma processing apparatus includes a vacuum chamber in which a semiconductor wafer is accommodated. In the chamber, a pair of electrodes are provided to face each other, and the wafer is placed on one electrode. Between a pair of the electrodes, a vertical electric field is formed, and a horizontal magnetic field is formed by the dipole ring magnet to cross perpendicularly to the electric field. The magnetic field has a gradient of the magnetic field intensity such that the intensity is high on the upstream side and is low on the downstream side in the electron-drift direction. Further, the magnetic field is formed such that the intensity is made uniform over a large area including the end portion of the wafer on the upstream side in the electron-drift direction and a region right outside it.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: February 20, 2001
    Assignee: Tokyo Electron Limited
    Inventors: Kazuhiro Kubota, Shigeki Tozawa, Jun Hirose, Akira Koshiishi, Tomomi Kondo
  • Patent number: 6187603
    Abstract: An electron-emitting device is fabricated by a process in which particles (46) are distributed over an initial structure. The particles are utilized in defining primary openings (52, 64, or 78) that extend through a primary layer (50A, 62A, or 72) provided over a gate layer (48A, 60A, or 60B) formed over an insulating layer (44) and in defining corresponding gate openings (54, 66, or 80) that extend through the gate layer. The insulating layer is etched through the primary and gate openings to form corresponding dielectric openings (56 or 68) through the insulating layer down to a lower non-insulating region (42). Electron-emissive elements (58A or 70A) are formed over the lower non-insulating region so that each electron-emissive element is at least partially situated in one dielectric opening.
    Type: Grant
    Filed: June 7, 1996
    Date of Patent: February 13, 2001
    Assignee: Candescent Technologies Corporation
    Inventors: Duane A. Haven, N. Johan Knall, Paul N. Ludwig, John M. Macaulay
  • Patent number: 6187214
    Abstract: Atomized particles within a desired size range (e.g., 1 micron to about 5 microns) are produced from two immiscible fluids, a first fluid source containing the formulation to be atomized, and a second fluid source which is contained in a pressure chamber surrounding at least the area where the first liquid is to be provided. The invention provides methods for: the production of templates for microfabrication, such as particles that serve as templates for self-assembly of monolayers; the creation of small particles to serve as building blocks for the microassembly of objects; and the use of an atomizate to etch configurations and/or patterns onto the surface of an object by removing a selected portion of the surface.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: February 13, 2001
    Assignee: Universidad de Seville
    Inventor: Alfonso Gañán-Calvo
  • Patent number: 6187688
    Abstract: After an organic bottom anti-reflective coating (12) is deposited on an underlying film (11), a resist pattern (15) is formed on the organic bottom anti-reflective coating (12). Dry etching is performed with respect to the organic bottom anti-reflective coating (12) masked with the resist pattern (15) to form an anti-reflective coating pattern. The dry-etching of the organic bottom anti-reflective coating (12) is performed by using etching gas containing gas having the S component such as SO2/O2-based etching gas or COS/O2-based etching gas.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: February 13, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Ohkuni, Shunsuke Kugo, Tomoyuki Sasaki, Kenji Tateiwa, Hideo Nikoh
  • Patent number: 6174815
    Abstract: A method for planarizing DRAM cells comprising the steps of providing a silicon substrate having a field oxide layer, an oxide layer and a capacitor formed thereon, then forming a first dielectric layer over the substrate. Next, portions of the first dielectric layer is etched back to form a spacer layer, and then a second dielectric layer is formed over the spacer layer. Thereafter, an insulating layer is formed over the second dielectric layer. Finally, the insulating layer is fully etched back to form a third dielectric layer.
    Type: Grant
    Filed: October 27, 1997
    Date of Patent: January 16, 2001
    Assignee: Vanguard Semiconductor Corp.
    Inventors: Fu-Liang Yang, Chau-Jen Kuo, Bin Liu
  • Patent number: 6174448
    Abstract: A method of removing a diffusion aluminide coating on a component designed for use in a hostile environment, such as superalloy turbine, combustor and augmentor components of a gas turbine engine. The method selectively removes an aluminide coating by stripping aluminum from the coating without causing excessive attack, alloy depletion and gross thinning of the underlying superalloy substrate. Processing steps generally include contacting the coating with a mixture that contains a halogen-containing activator and a metallic powder containing an aluminide-forming metal constituent, such as by pack cementation-type process. The mixture is then heated to a temperature sufficient to vaporize the halogen-containing activator and for a duration sufficient to cause the halogen-containing activator to provide a transfer mechanism for the removal of aluminum from at least a portion of the diffusion aluminide coating, while the metallic powder absorbs the removed aluminum.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: January 16, 2001
    Assignee: General Electric Company
    Inventors: Nripendra N. Das, Howard J. Farr, Raymond W. Heidorn
  • Patent number: 6171514
    Abstract: A polishing method for planarizing a substrate which provides an efficient polishing so that a time needed for polishing is reduced as compared to the conventional method. A first polishing process removes a portion of a polish stop layer that covers a high area by using a first slurry having a high polishing capability against the polish stop layer. A second polishing process, subsequent to the first polishing process, removes the high area by using a second slurry having a high polishing capability for polishing a material covered by the polish stop layer. A polishing capability of the second slurry for polishing the polish stop layer is lower than the polishing capability of the first slurry for polishing the polish stop layer.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: January 9, 2001
    Assignee: Fujitsu Limited
    Inventors: Kouichi Hara, Norikazu Ozaki
  • Patent number: 6168725
    Abstract: The invention is an aluminum etchant and method for chemically milling aluminum from, according to a preferred embodiment, a copper-aluminum-copper tri-metal layer to form three-dimensional circuits. The tri-metal comprises copper circuit patterns present on opposing surfaces of an aluminum foil, one of the copper patterns being laminated on a substrate. The etchant comprises an aqueous solution of 60 to 500 g/l base selected from (a) sodium hydroxide, (b) potassium hydroxide, and (c) their mixture; and 30 to 500 g/l of an additive selected from nitrite salt, a borate salt, a bromate salt, or mixture of any of them. The method comprises contacting the tri-metal with the etchant at a temperature between 25 and 95° C. for a time sufficient to remove a desired amount of the aluminum layer and provide (rigid, flexible, or 3-dimensional) electronic circuitry which may contain multiple conductive circuit layers.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: January 2, 2001
    Assignee: Visteon Global Technologies, Inc.
    Inventors: Achyuta Achari, Mohan R. Paruchuri