Abstract: A system includes a control system and a Remote Terminal Unit (RTU). The control system is configured to communicate data with one or more field devices via the RTU. The RTU is configured to transmit received data from the one or more field devices and the control system. The RTU is also configured to activate a power saving mode that selectively provides power to transmit the received data. The RTU is further configured to, while the power saving mode is activated, prevent power from being provided to transmit the received data, and store the received data in a memory of the RTU when the power is not provided to transmit the received data. The RTU is configured to, while the power saving mode is activated, provide power to transmit the received data after storing the received data in the memory of the RTU.

Abstract: Embodiments herein relate to loading boot data. In an embodiment, a device loads boot data from a first portion of a first non-volatile memory to complete a first booting of the device. The first portion of the first non-volatile memory is then released to allow the device to overwrite the first portion. Next, the boot data is written to the first non-volatile memory before the device enters a reduced power state. The written boot data is to be loaded from the first non-volatile memory to complete a second booting of the device, if the second booting is initiated.

Abstract: Embodiments of a device and method to automatically acquire signal quality metrics in a digital communication system are disclosed. The device may include acquisition means to sample the likelihood of a digital communication signal passing through a grid of time and amplitude regions, and storage means by which such likelihood measurements may be accumulated in a computer memory array for analysis. A state machine may execute a method that controls both the acquisition means and the storage means, requiring minimal intervention from supervisory systems.

Abstract: A computer implemented method includes identifying in an original circuit output signals that drive domain crossing logic separating a first clock domain from a second clock domain. A revised circuit is formed with a register attached to the domain crossing logic. The register receives an output signal and a synchronization signal that precludes the output signal from transitioning at selected clock cycle intervals.

Abstract: The present invention provides a method of easily managing two or more OSs. A host OS, a guest OS, and a virtualization module are loaded into a primary physical address area of a main memory. The guest OS is executed in a virtual environment in a primary physical address area. A memory image of the guest OS loaded in the primary physical address area is copied to a secondary physical address area. The right of access to a processor is transferred to the guest OS copied in the secondary physical address area to execute the guest OS in a physical environment.

Abstract: Serial peripheral interfaces and methods of operating the same are provided. An apparatus can have a serial peripheral interface (SPI) including a first command state machine (CSM), and a second CSM.

Abstract: A controller and a method for power sequencing a computer. The controller may be configured to provide to a south bridge, before the south bridge has completed power management resets, a real time clock signal at a first frequency, and provide to the south bridge, after the south bridge has completed power management resets, a real time clock signal at a second frequency.

Abstract: A power management method and apparatus, and a power supply system are provided. The method includes: obtaining a power demand value of each module and a rated output power of each power supply unit (PSU) in a communication equipment; calculating the obtained power demand value of each module to acquire a total power demand value of the modules; and adjusting, according to the calculated total power demand value of the modules and the obtained rated output power of each PSU, the current number of the PSUs actually turned on in the communication equipment.

Abstract: Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.

Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Abstract: Technologies are generally described to provide a leakage current variability based power management of a processor. According to some examples, instruction counters and aggregated power consumption of the processor may be used to process power measurements of the processor into linear equations. The linear equations may be processed to produce a set of leakage values for the processor. In an example scenario, computation data from a power controller and processor instruction counters (PICs) of a core of the processor may be used to determine the leakage current variability of the core. A table of linear combination samples may be generated from the computation data. A micro-architectural leakage map of the core may be generated from the linear combination samples within the table.

Abstract: A computing system is associated with power consumption based on Power over Ethernet (PoE). Power consumption is compared to a threshold, and a signal is asserted that power consumption is to be limited based on the comparison to the threshold.

Abstract: A power excursion warning system includes a power system having a first slew rate. A powered component is coupled to the power system. The powered component voltage regulator has a second slew rate that is greater than the first slew rate. A powered component voltage regulator is coupled to the powered component and operable to convert a first voltage received from the power system to a second voltage that is supplied to the powered component. A power excursion warning device is coupled to the powered component voltage regulator and operable to receive a signal from the powered component voltage regulator that is associated with the second slew rate, determine that the signal indicates a power excursion that will result in the power system operating outside a predetermined range, and produce a warning signal indicative of the power excursion.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: A method for controlling a sensor includes steps of: sensing an object for determining whether the object is within a sensing range of the sensor; if it is determined that the object is not within the sensing range, the sensor is turned into a non-active mode for a predicted non-active time, wherein the predicted non-active time is calculated based on a predetermined or a historical non-active time; sensing the object for determining whether the object is within the sensing range during the predicted non-active time; and if it is determined that the object is not within the sensing range during the predicted non-active time, the sensor is turned into a sleep mode for an predicted sleep time, wherein the predicted sleep time is calculated based on the predetermined non-active time and a predetermined sleep time, or is calculated based on the historical non-active time and a historical sleep time.

Abstract: The present invention relates to methods and systems for providing reliable power to a storage device, such as a network attached storage. In one embodiment, the storage device employs a redundant power backplane design using a DC-to-DC converter per drive in the backplane. Each drive is thus provided its own independent power interface to the power backplane. One embodiment may employ DC-to-DC converters having integrated N-channel MOSFETs to provide overcurrent and thermal protection. In addition, an embodiment may employ a staggered startup procedure to manage peak power draw.

Abstract: A real-time insulation detector for feeding a high-frequency low-voltage signal is electrically connected with a power system, and the power system includes a power circuit comprised of a main power circuit and plural branch circuits, a plurality of power transformers are arranged in the main power circuit and the plural branch circuits, and each current power transformer has a positive electrode point and a negative electrode point arranged on a low-voltage side thereof, the real-time insulation detector contains a central controller, a signal generator, a circuit selector, a plurality of detection circuits, plural first safety circuits, and plural second safety circuits. Thereby, the real-time insulation detector automatically feeds a high-frequency low-voltage detection signal, and when the power system runs in an uninterruptible power network, the central controller judges aging insulation comes from which one cable or component of the power system.

Abstract: Methods and apparatus for managing sideband segments in an On-Die System Fabric (OSF) are described. In one embodiment, a sideband OSF includes a plurality of segments that may be reset or powered down independently after power management logic determines that in progress messages have been handled and future messages to the segment being reset or powered down will be blocked. Other embodiments are also disclosed.

Abstract: Systems and methods are disclosed for providing auxiliary reserve current to power a system load of an information handing system using an auxiliary energy storage power source as an energy cache to selectably provide auxiliary reserve current to at least partially supplement the normal operating power supply (e.g., battery pack, AC adapter, AC/DC power source, etc.) of an information handling system during temporary times of increased current need by the system load of the information handling system.

Abstract: A processor having a multi-Vt critical path is provided that includes both low-Vt devices and high-Vt devices. If the processor is operating in a high performance mode, the multi-Vt critical path is controlled so as to use the low-Vt devices. Conversely, if the processor is operating in a low power mode, the multi-Vt critical path is controlled so as to use the high-Vt devices. In this fashion, the complication of multiple processing cores is avoided in that a single processor core can operate in both the high performance mode and in the low power mode.