Abstract: Conventional receiver architectures are based on either frequency/phase tracking or oversampling. Both receiver types typically employ sensitive analog circuits, which create noise, consume power and utilize valuable space in their implementation. The invention adopts a novel approach to phase/frequency tracking that utilizes the edges or zero crossings of the input data waveform to effectively track the remote transmitter clock phase/frequency. This methodology minimizes the use of analog circuitry, thereby reducing the noise domain and the substrate space required for implementation of a tracking device.

Abstract: Each of first and second stations, in communicating with the other station, provides a preamble including forward link parameters and reverse link parameters. The forward link parameters in each preamble for each individual station are provided for each station in accordance with the reverse link parameters previously transmitted to the station in packets from the other station. The reverse link parameters in each preamble in each individual station provide an indication to the other station of the forward link parameters to be provided by the other station in the next transmission of a packet to the individual station from the other station. Data is provided in packets at each station to be transmitted to the other station. Each packet transmitted by each station to the other station includes a preamble and includes data after the preamble.

Abstract: A method for coherent phase synchronous CDMA communications between a gateway and multiple subscribers via multiple transponder platforms that includes the step of synchronizing a local reference clock for each subscriber in a service area to a single master reference clock for multiple transponder platforms wherein the distance separating the transponder platforms is constrained to a range wherein the local reference clocks for all subscribers have substantially the same phase with respect to the master reference clock.

Abstract: A digital and a multiplication method are described, which lead to an efficient architecture for a hardware implementation of digital FIR and IIR filters into FPGAs. The multiplications of input sample data and delayed sample data with filter coefficients are performed by addressing look-up tables in which corresponding multiplication results are prestored. The size of the look-up tables is reduced by storing only those multiplication results which cannot be obtained by a shifting operation performed on the other pre-stored multiplication results, the input sample data, or the delayed sample data. Thereby, the size of the look-up tables can be compressed significantly such that an implementation of large digital filters into FPGAs is possible.

Abstract: A receiver for the CDMA system, in order to reduce a power consumption during a suspension period of intermittent receiving operation, monitors a suspension period t1 by means of a low-power timer 51 so that a VC-TCXO 1, a reference signal group generation unit 2 and a receiving unit 3 are turned off and a modem unit 4 is set to a sleep state. Upon resumption of receiving operation, a high-accuracy timer 44 is supplied with a start (d) to require counting of time t3 and a part of a received signal is stored. A PN code phase of stored data is calculated in a PN code phase calculator 46 during a period t3 to obtain an indication value i for a phase deviation. State vectors for short code and long code and further a reception time t4 are calculated on the basis of the indication value i to be set.

Abstract: A demodulator for automatically performing quadrature control in which there is no necessity for the modulator side to perform precision adjustment and deterioration in characteristics e.g., error rate is suppressed for long.

Abstract: The invention relates to a method of processing multipath-propagated components of a signal in a communications system. In the method, a signal transmitted on the radio channel of the communications system is received in a RAKE receiver and an impulse response of the radio channel is formed. In the method, one or more taps having the highest signal energy in the impulse response are located and matched to a short matched filter. A weighting value for the impulse response is calculated on the basis of the one or more taps in the matched filter and a deviation between the weighting value and the center point of the matched filter is compared with a threshold value set for the deviation. The matched filter is moved toward the deviation when the deviation exceeds the threshold value set for the deviation.

Abstract: A system, method, and computer program product for removing “narrowband” interference from a broader spectrum containing a UWB signal, in a receiver of the UWB signal. The RFI is extracted from a broader spectrum to remove interference from the UWB signal, by employing an impulse response in a radio front-end of the UWB receiver that is matched with an incoming wavelet employed as part of a UWB signal to be received, matching the impulse response to the wavelet and its time-shifted and inverted versions, passing the wavelet unscathed through the receiver, and excising narrowband signals (continuous tones). Exemplary embodiments for the RFI extraction mechanism include a transmission line circuit, an active transmission line circuit, and an adaptable, controllable phase delay circuit.

Abstract: A quadrature amplitude modulation implementation incorporating a symmetric spherical quadrature amplitude modulation constellation. The symmetric spherical quadrature amplitude constellation, as displayed in a multi-dimensional complex plane, is bounded by a surface comprising all symbol points at a predetermined distance from a center point and coincident with the intersection of at least two axes, and exhibiting correspondence in relative position of the symbol points on opposite sides of the at least two axes.

Abstract: An apparatus and method for OFDM demodulation establish symbol synchronization to minimize between-symbol interference even under an environment where multipath occurs. An incoming signal is an OFDM signal including a transmission symbol structured by a valid symbol period and a guard interval, and a predetermined synchronization symbol is included in the OFDM signal for every transmission frame. A correlator calculates how a signal generated by a synchronization symbol generator and the OFDM signal are correlated. A correlation calculator then calculates a correlation therefrom. An integrator integrates the calculated correlation by the guard interval. A timing determination device determines symbol timing from the integrated correlation. An FFT window generator outputs operation timing for Fourier transform from the determined symbol timing.

Abstract: For encoding a source sequence of symbols (u) as an encoded sequence, the source sequence (u) is divided into p1 first sub-sequences (Ui), p1 being a positive integer, and each of the first sub-sequences (Ui) is encoded in a first circular convolutional encoding method. The source sequence (u) is interleaved into an interleaved sequence (u*), and the interleaved sequence (u*) is divided into p2 second sub-sequences (U?i), p2 being a positive integer. Each of the second sub-sequences (U?i) is encoded in a second circular convolutional encoding method. At least one of the integers p1 and p2 is strictly greater than 1 and at least one of the first sub-sequences (Ui) is not interleaved into any of the second sub-sequences (U?j). (It is noted that the above underlining of the following symbols is original, and is meant to be permanent: u, Ui, u*, U?i, U?j).

Abstract: An apparatus comprising an analog circuit and a digital circuit. The analog circuit may be configured to generate a plurality of samples of an input signal in response to a plurality of phases of a reference clock. The digital circuit may be configured to (i) measure a width of a symbol in the input signal in response to the plurality of samples and the plurality of phases of the reference clock and (ii) adjust the measured width in response to a correction signal.

Abstract: A method of frame synchronization for serial data transmission is presented herein. A transmitting circuit in a data communication apparatus converts frame data into serial data and transmits the same, and following the serial data, the transmitting circuit transmits frame synchronization data varying several times in the interval from an edge of a clock signal to an edge of the next clock signal; a receiving circuit receives the frame data and detects two or more variations in the same interval to find the end of the frame data, by receiving the serial data from a signal line, serial data is transmitted while carrying out frame synchronization.

Abstract: A system that detects and corrects for phase offset between a subscriber and a service provider. The phase offset detection and correction system provides for improved performance of Pulse Code Modulation encoding in the upstream direction.

Abstract: A method and an apparatus for a channel estimator comprising a plurality of distinct filters each of which has a set of different coefficients and each of which is selectively coupled to the input and output of the channel estimator. The channel estimator further comprises a switching circuit that receives an error signal and switches to one of the plurality of filters based on the value of the error signal relative to an established threshold. The error signal is from a decoder coupled to a communication channel whose response is being estimated by the apparatus and method of the present invention.

Abstract: A data extracting circuit extracts data much more accurately at a much higher response speed. A clock transfer section propagates an input clock signal through unit delay devices thereof. An edge detecting section locates an edge of the clock signal, which edge is being propagated through the clock transfer section, for a time represented by a given edge of an input data signal. In response to an edge detection signal indicating the clock signal edge located, a clock selecting section selects one of outputs of the delay devices, and presents the output as a clock input to a latch.

Abstract: A digital data storage (DDS) system for reading DDS tapes employs a partial response maximum likelihood detection system which utilises redundancy in the 8-10 DC free modulation encoding to reduce low frequency noise. The system incorporates a time-varying trellis decoder which embodies some of the PR1 rules together with the rules regarding the charge state or the digital sum variation (DSV) implicit in 8-10 modulation coding. The decoder operates to reject low frequency noise such as that caused by crosstalk noise between adjacent tracks on the tape. The trellis topography has been considerably simplified by adopting a two step six state trellis which operates on bit pairs and in which the states relate to the current DSV value, and sign of the previous bit.

Abstract: A filter arrangement with a linear phase characteristic having first filter cascade coupled to second filter. The first filter is an analog or digital filter designed so that its amplitude characteristic meets a predefined amplitude specification. The second filter is implemented as the anti-causal version of a fictive digital all-pass filter that is designed so that its phase characteristic, up to a linear function of frequency, equals the phase characteristic of the first filter.

Abstract: A wireless radiofrequency data communication system has a base-station with N first groups and a signal processing-unit with a memory and processor. Each first group has a receiver-unit provided with a receiver and at least one antenna which is connected to the receiver-unit, and the signal processing-unit is connected with each of the first groups for processing receive-signals generated by each of the first groups. The base station further has M second groups for transmitting radiofrequency signals to the first groups. Each second group has a transmitter-unit provided with a transmitter and at least one antenna which is connected to the transmitter-unit. The memory of the signal processing-unit is provided with information about the transfer-functions of radiofrequency signals from each of the antennas of the second groups to each of the antennas of the first groups, and the transmitters and receivers operate on essentially the same radio frequency or radiofrequency-band.

Abstract: A method and apparatus for initial acquisition using an adaptive threshold includes performing a sort operation of a plurality of full-length correlator outputs and updating the adaptive threshold. Partial-length correlator outputs are generated and compared with an adaptive threshold. If a partial-length correlator output for a particular PN sequence timing is greater than or equal to the adaptive threshold, a full-length correlator output for that PN sequence timing is generated. A sort operation of a plurality of full-length correlator outputs is performed, and sort results are used to update the adaptive threshold. If a partial-length correlator output for a particular PN sequence timing is less than the adaptive threshold, a full-length correlator output for that PN sequence timing is not generated.