Abstract: A metrology target for use in measuring misregistration between layers of a semiconductor device including a first target structure placed on a first layer of a semiconductor device, the first target structure including a first plurality of unitary elements respectively located in at least four regions of the first target structure, the first plurality of elements being rotationally symmetric with respect to a first center of symmetry and at least a second target structure placed on at least a second layer of the semiconductor device, the second target structure including a second plurality of elements respectively located in at least four regions of the second target structure, the second plurality of elements being rotationally symmetric with respect to a second center of symmetry, the second center of symmetry being designed to be axially aligned with the first center of symmetry and corresponding ones of the second plurality of elements being located adjacent corresponding ones of the first plurality of e

Abstract: In method for forming a semiconductor device, a first opening is formed in a dielectric stack that has a cylinder shape with a first sidewall. A first conductive layer is deposited along the first sidewall of the first opening and a first insulating layer is deposited along an inner sidewall of the first conductive layer. The dielectric stack is then etched along an inner sidewall of the first insulating layer so as to form a second opening that extends into the dielectric stack with a second sidewall. A second conductive layer is further formed along the second sidewall of the second opening and a second insulating layer is formed along an inner sidewall of the second conductive layer. A bottom of the second conductive layer is positioned below a bottom of the first conductive layer to form a staggered configuration.

Abstract: A semiconductor package is disclosed. In one example, the semiconductor package includes a chip carrier, a semiconductor chip attached to the chip carrier, an encapsulation body encapsulating the semiconductor chip, and a mounting hole configured to receive a screw for screw mounting a heatsink onto a first side of the semiconductor package. A second side of the semiconductor package opposite the first side is configured to be surface mounted to an application board.

Abstract: A high-frequency device includes a second substrate disposed opposite to a first substrate, a first electrode disposed on a side surface of the first substrate adjacent to the second substrate, a second electrode disposed on a side surface of the second substrate adjacent to the first substrate, a sealant disposed between the first substrate and the second substrate, and a dielectric layer sandwiched between the first substrate and the second substrate by the sealant. The dielectric layer includes a gas or vacuum.

Abstract: A piezoelectric actuator is formed like a rectangular flat plate, and includes a substrate layer, a lower electrode layer, a piezoelectric layer, and an upper electrode layer formed in this order from bottom to top in a thickness direction. The upper electrode layer is constituted of a plurality of electrode segments separated in a surface direction, and connection wires connecting the electrode segments which are adjoining in the surface direction.

Abstract: A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

Abstract: A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.

Abstract: A method of forming an integrated circuit includes placing a first cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on the layout design. Placing the first cell layout design includes placing a first active region layout pattern adjacent to a first cell boundary, placing a second active region layout pattern adjacent to a second cell boundary, and placing a first set of active region layout patterns between the first and second active region layout patterns, according to a first set of guidelines. The first set of guidelines includes selecting transistors of a first type with a first driving strength and transistors of a second type with a second driving strength. In some embodiments, the first, second and first set of active region layout patterns extend in the first direction, and are on a first layout level.

Abstract: An integrated circuit (IC) device includes a plurality of first TAP cells of a first semiconductor type, and a plurality of second TAP cells of a second semiconductor type different from the first semiconductor type. The plurality of first TAP cells is arranged in at least two columns, the at least two columns adjacent each other in a first direction and extending in a second direction transverse to the first direction. Each of the plurality of first TAP cells has a first length in the first direction. The plurality of second TAP cells includes at least one second TAP cell extending in the first direction between the at least two columns over a second length greater than the first length of each of the plurality of first TAP cells in the first direction.

Abstract: A microprocessor mounting apparatus comprising a microprocessor socket on a printed circuit board (PCB) and a bolster plate surrounding a perimeter of the microprocessor socket. The bolster plate has a first surface adjacent to the PCB, and a second surface opposite the first surface. A heat dissipation device is on the second surface of the bolster plate. The heat dissipation interface is thermally coupled to the microprocessor socket.

Abstract: First and second memory cells are arranged on a semiconductor substrate. The memory cell includes, between a first or second source region and a first or second drain, a configuration in which a first or second selection gate and a first or second floating gate are arranged in series. The first memory cell and the second memory cell are adjacent to each other in a first direction. A first signal line extending in the first direction and connected to the first and second selection gates is further provided. The first and second source regions are configured to share a first region. The first selection gate extends in a direction different from the first direction.

Abstract: The present application provides a semiconductor device. The semiconductor device includes a bonding pad disposed over a semiconductor substrate; a first spacer disposed over a top surface of the bonding pad; a second spacer disposed over a sidewall of the bonding pad; a dielectric layer between the bonding pad and the semiconductor substrate. The dielectric layer includes silicon-rich oxide; and a conductive bump disposed over the first passivation layer. The conductive bump is electrically connected to a source/drain (S/D) region in the semiconductor substrate through the bonding pad. The semiconductor device also includes a dielectric liner disposed between the first spacer and the bonding pad; and a first passivation layer covering the second spacer, wherein the dielectric liner is L-shaped, and the first spacer is separated from the bonding pad by the dielectric liner.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a transistor region, a metal interconnect, and a magnetic tunneling junction (MTJ). The transistor region includes a gate over the substrate, and a doped region is at least partially in the substrate. The metal interconnect is over the doped region. The metal interconnect includes a metal via. The MTJ is entirely underneath the metal interconnect and between the doped region and the metal via, and a diameter of a bottom surface of the MTJ is greater than a diameter of an upper surface of the MTJ.

Abstract: A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

Abstract: A method for forming a chip package structure is provided. The method includes forming a conductive pad over a carrier substrate. The method includes forming a substrate layer over the carrier substrate, wherein the conductive pad is embedded in the substrate layer, and the substrate layer includes fibers. The method includes forming a through hole in the substrate layer and exposing the conductive pad. The method includes forming a conductive pillar in the through hole. The method includes forming a recess in the substrate layer. The method includes disposing a chip in the recess. The method includes forming a molding layer in the recess. The method includes forming a redistribution structure over the substrate layer, the conductive pillar, the molding layer, and the chip. The method includes removing the carrier substrate.

Abstract: Semiconductor structures are provided. Each transistor includes a first source/drain region over a semiconductor fin, a second source/drain region over the semiconductor fin, a channel region in the semiconductor fin and between the first and second source/drain regions, and a metal gate electrode formed on the channel region and extending in a second direction. In a first transistor of the transistors, the first source/drain region is formed between the metal gate electrode of the first transistor and the metal gate electrode of a second transistor of the transistors. The second source/drain region is formed between the metal gate electrode of the first transistor and the dielectric-base dummy gate. A first contact of the first source/drain region is separated from a spacer of the metal gate electrode of the first transistor. A second contact of the second source/drain region is in contact with a spacer of the dielectric-base dummy gate.

Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Abstract: A three-dimensional semiconductor memory device is disclosed. The device may include a substrate including a cell array region and a connection region provided at an end portion of the cell array region, an electrode structure extending from the cell array region to the connection region, the electrode structure including electrodes sequentially stacked on the substrate, an upper insulating layer provided on the electrode structure, a first horizontal insulating layer provided in the upper insulating layer and extending along the electrodes, and first contact plugs provided on the connection region to penetrate the upper insulating layer and the first horizontal insulating layer. The first horizontal insulating layer may include a material having a better etch-resistive property than the upper insulating layer.

Abstract: A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.