Patents Examined by Amir Zarabian
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Patent number: 8547750Abstract: Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the adjacent data line is maintained at the particular voltage. Various embodiments include the array architecture to facilitate precharging the adjacent pair of data lines to a particular voltage and maintaining the unselected data line at the particular voltage during a sensing phase of a read operation.Type: GrantFiled: April 7, 2011Date of Patent: October 1, 2013Assignee: Micron Technology, Inc.Inventor: Aaron Yip
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Patent number: 8493781Abstract: A method for data storage includes accepting data for storage in a memory that includes multiple analog memory cells. The data is stored in a first group of the memory cells by programming a second group of the memory cells so as to cause the second group to generate interference in the first group, and individually erasing the first group while verifying that analog levels of the memory cells in the first group subject to the interference are within a predefined bound following erasure. After erasing the first group, the first group of the memory cells is programmed with the data.Type: GrantFiled: July 28, 2011Date of Patent: July 23, 2013Assignee: Apple Inc.Inventors: Avraham Meir, Eyal Gurgi, Ronen Dar, Naftali Sommer, Ofir Shalvi
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Patent number: 8391053Abstract: A magnetic random access memory (MRAM) cell with a thermally assisted switching (TAS) writing procedure, comprising a magnetic tunnel junction formed from a ferromagnetic storage layer having a first magnetization adjustable at a high temperature threshold, a ferromagnetic reference layer having a fixed second magnetization direction, and an insulating layer, said insulating layer being disposed between the ferromagnetic storage and reference layers; a select transistor being electrically connected to said magnetic tunnel junction and controllable via a word line; a current line electrically connected to said magnetic tunnel junction; characterized in that the magnetocrystalline anisotropy of the ferromagnetic storage layer is essentially orthogonal with the magnetocrystalline anisotropy of the ferromagnetic reference layer. The TAS-MRAM cell of the invention can be written with a smaller magnetic field than the one used in conventional TAS-MRAM cells and has low power consumption.Type: GrantFiled: May 4, 2010Date of Patent: March 5, 2013Assignee: Crocus Technology SAInventors: Ioan Lucian Prejbeanu, Clarisse Ducruet
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Patent number: 8363488Abstract: In a method of operating a reference voltage regulator for an embedded dynamic random access memory (eDRAM) employing VSS-sensing with a reference level, an oscillator sends requests for sampling and correction to a control block between accesses of the eDRAM. The control block sends a pulse defining a time interval during which sampling and correction occurs to a pulse generator. A reference generator provides the reference level to a comparator. The comparator compares the reference level with a sampling of a reference voltage to decide if the reference voltage requires correction. The comparator sends a correction request to a pulse generator if the reference voltage requires correction. The pulse generator generates a correction pulse for a driver according to the correction request from the comparator. The driver adjusts the reference voltage during the correction pulse.Type: GrantFiled: October 4, 2011Date of Patent: January 29, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Muhammad Nummer, Sergiy Romanovskyy
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Patent number: 8358548Abstract: A test system and a method for efficiently repairing marginally failing memory cells in an embedded dynamic random access memory on an integrated circuit identify marginally failing cells in the embedded memory and when two or more marginally failing cells are located in the same column, indicating a partial column failure due to a weak sense amplifier associated with the column, the system and method apply a spare column preferentially to repair the failing cells in the column. The test system can be arranged in a built-in self test engine on the integrated circuit. In an alternative embodiment, the test system can be implemented in test equipment coupled to the integrated circuit that houses the embedded dynamic random-access memory.Type: GrantFiled: October 19, 2009Date of Patent: January 22, 2013Assignee: Avago Technologies Enterprise IP (Singapore) Pte. Ltd.Inventors: Indrajit Manna, James Pfiester, David Leary
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Patent number: 8305713Abstract: This application discloses a Load-UnLoad (LUL) hard disk drive comprising a disk base, a spindle motor mounted on the disk base for rotating at least one disk to create at least one rotating disk surface, and a head stack assembly pivotably coupled to the disk base and configured to engage an actuator latch when the sliders of the head stack assembly are to be parked. The actuator latch includes a latch beam coupled through a latch pivot to the disk base and a boss coupled to the latch beam and configured to limit the stroke of latch motion in the event of a rotary non-operational shock.Type: GrantFiled: May 6, 2009Date of Patent: November 6, 2012Assignee: Seagate Technology InternationalInventors: Tomokazu Ishii, Seong Woo Kang, Seungman Chang, Chaw-Wu Tseng
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Patent number: 8107195Abstract: A first sleeve rotatably extends around a shaft. First and second flanges are fixed to the shaft. A second sleeve extending around the first sleeve is fixed thereto. A first annular member fixed to the second sleeve surrounds the first flange. A second annular member fixed to the second flange surrounds a portion of the second sleeve. A first capillary seal includes a clearance between the first flange and the first annular member. A second capillary seal includes a clearance between the second annular member and the second sleeve. Lubricant is provided in the clearances in the first and second capillary seals. The second annular member and the second sleeve are designed so that the lubricant in the clearance in the second capillary seal can be viewed from a point in a radial position which is outward of the second sleeve as seen in an axial direction.Type: GrantFiled: May 1, 2009Date of Patent: January 31, 2012Assignee: ALPHANA Technology, Co., Ltd.Inventor: Ryusuke Sugiki
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Patent number: 8108650Abstract: In an embodiment, a TLB is partitioned into regions. The TLB may be set associative, and each section may include a portion of the locations in each way of the set associative memory. The TLB may reserve at least one of the sections for access by a subset of the request sources that use the TLB. For requests from the subset, the reserved section may be used and a location in the reserved section may be allocated to store a translation for a request from the subset that misses in the TLB. For requests for other request sources, the non-reserved section or sections may be used. In one embodiment, each way of the reserved section may be assigned to a different one of the request sources in the subset.Type: GrantFiled: May 29, 2009Date of Patent: January 31, 2012Assignee: Apple Inc.Inventor: Joseph A. Petolino, Jr.
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Patent number: 8094508Abstract: A memory block of a memory device is tested by programming a plurality of pages of the memory block, passing the memory block if a number of pages, each programmed in a first programming time, is greater than or equal to a first predetermined number and a number of pages, each programmed in a second programming time, is less than or equal to a second predetermined number, and failing the memory block if a programming time of any one of the pages exceeds a predetermined programming time or if the number of pages programmed in the first programming time is less than the first predetermined number or if the number of pages programmed in the second programming time exceeds the second predetermined number.Type: GrantFiled: July 27, 2009Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventors: Scott N. Gatzemeier, Joemar Sinipete, Nevil Gajera, Mark Hawes
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Patent number: 8094507Abstract: Examples of command latency systems and methods are described. In some examples, phase information associated with a received command signal is stored, a received command signal is propagated through a reduced clock flip-flop pipeline and the delayed command signal is combined with the stored phase information. The reduced clock flip-flop pipeline may use a clock having a lower frequency than that used to issue the command signal. Accordingly, fewer flip-flops may be required.Type: GrantFiled: July 9, 2009Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventor: Don Morgan
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Patent number: 8089822Abstract: A circuit and method are provided for controlling power consumption in an electronic circuit. Generally, the method involves measuring current flow through a memory core in the circuit, the memory core including a number of cells each with a number of active devices, and, if current flow exceeds a predetermined amount limiting it by applying reverse body bias to the active devices. In one embodiment, power is supplied to the memory through a low drop-out (LDO) regulator fabricated on a common substrate therewith, and the LDO regulator functions as a current mirror to mirror current through the memory core through a replica stack. Other embodiments are also disclosed.Type: GrantFiled: February 12, 2007Date of Patent: January 3, 2012Assignee: Cypress Semiconductor CorporationInventors: Talluri V. Chankya, V. Sambasiva Rao
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Patent number: 8081502Abstract: An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.Type: GrantFiled: December 29, 2008Date of Patent: December 20, 2011Assignee: Altera CorporationInventors: Irfan Rahim, Jun Liu, Andy L. Lee, William Bradley Vest, Lu Zhou, Qi Xiang, Yanzhong Yu, Jeffrey Xiaoqi Tung, Albert Ratnakumar
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Patent number: 8072824Abstract: An operation guarantee system includes a decoder circuit, a comparison circuit, a CPU circuit, a frequency adjustment circuit and a DQ adjustment circuit. The comparison circuit compares a test data signal input from the decoder circuit with an expected value data signal input from the exterior, and detects the presence or absence of an output error in the decoder circuit. The CPU circuit controls the frequency adjustment circuit and the DQ adjustment circuit to vary a frequency of a clock signal input to an external memory and a delay amount of the data signal. In addition, the CPU circuit acquires a result of detection of the comparison circuit under various conditions. Then, the CPU circuit determines an appropriate frequency of the clock signal input to the external memory based on a relationship between the various conditions and the presence or absence of the output error.Type: GrantFiled: June 27, 2008Date of Patent: December 6, 2011Assignee: Panasonic CorporationInventor: Masahiro Takatori
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Patent number: 8059442Abstract: Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.Type: GrantFiled: August 11, 2010Date of Patent: November 15, 2011Assignee: Atmel CorporationInventors: Salwa Bouzekri Alami, Lotfi Ben Ammar
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Patent number: 8059354Abstract: An apparatus includes a metallic transducer and a condenser for directing electromagnetic radiation onto the transducer. The transducer includes a first section and a second section, wherein the first section is wider than the second section and has a width to length aspect ratio greater than or equal to a width to length aspect ratio of the second section, the first section having a dimple formed on a surface thereof.Type: GrantFiled: January 29, 2009Date of Patent: November 15, 2011Assignee: Seagate Technology LLCInventor: Amit Vasant Itagi
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Patent number: 8050104Abstract: A non-volatile memory device and system are provided. The non-volatile memory device including; a memory cell array of memory blocks, and a bit line bias block connected to the bit lines and configured to precharge the bit lines, a page buffer precharging the plurality of bit lines and sensing data stored in the memory block via the bit lines, and a controller controlling the bit line bias block to simultaneously precharge the bit lines with the page buffer, thereby reducing the bit line bias time.Type: GrantFiled: February 1, 2010Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Dae Seok Byeon
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Patent number: 8045392Abstract: The programming method of the present invention minimizes program disturb by initially programming cells on the same word line with the logical state having the highest threshold voltage. The remaining cells on the word line are programmed to their respective logical states in order of decreasing threshold voltage levels.Type: GrantFiled: May 22, 2008Date of Patent: October 25, 2011Assignee: Round Rock Research, LLCInventor: Hagop A. Nazarian
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Patent number: 8036021Abstract: A memory cell array includes a plurality of memory cells arranged at intersections of bit line pairs and word lines. Each memory cell includes a first transistor having one main electrode connected to a first bit line, a second transistor having one main electrode connected to a second bit line, a first node electrode for data-storage connected to the other main electrode of the first transistor, a second node electrode for data-storage connected to the other main electrode of the second transistor, and a shield electrode formed surrounding the first and second node electrodes. The first and second transistors have respective gates both connected to an identical word line, and the first and second bit lines are connected to an identical sense amp. The first and second node electrodes, the first and second bit lines, the word line and the shield electrode are isolated from each other using insulating films.Type: GrantFiled: November 18, 2009Date of Patent: October 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryo Fukuda, Daisaburo Takashima
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Patent number: 8036016Abstract: Subject matter disclosed herein relates to enhancing an operational lifespan of non-volatile memory.Type: GrantFiled: September 1, 2009Date of Patent: October 11, 2011Assignee: Micron Technology, Inc.Inventors: Joy Sarker, Robert Gleixner
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Patent number: 8031525Abstract: A flash memory device that includes a voltage generator circuit configured to generate a program voltage, a pass voltage, and a high voltage; a plurality of planes configured to perform a program operation in response to the program, pass, and high voltages and to verify the program operation, respectively; and control logic configured to control the planes in response to verification results from the planes, wherein the control logic controls the planes so as to interrupt the program and pass voltages or the high voltage from being applied to program-passed planes.Type: GrantFiled: April 10, 2008Date of Patent: October 4, 2011Assignee: Samsung Electronics Co., Ltd.Inventor: Jin-Sung Park