Abstract: A nitridation treatment method is provided. The nitridation treatment method includes executing a nitridation treatment with respect to a hydrophobic surface defining an interconnect trench to convert the hydrophobic surface to a hydrophilic surface. The nitridation treatment method further includes depositing a seed layer including a conductive material and manganese on the hydrophilic surface. The nitridation treatment method also includes thermally driving all the manganese out of the seed layer to form a diffusion barrier including manganese at the hydrophilic surface. In addition, the nitridation treatment method includes filling remaining space in the interconnect trench with the conductive material to form an interconnect.

Abstract: The light emitting element is provided to comprise: a first conductive type semiconductor layer; a mesa; a current blocking layer; a transparent electrode; a first electrode pad and a first electrode extension; a second electrode pad and a second electrode extension; and an insulation layer partially located on the lower portion of the first electrode, wherein the mesa includes at least one groove formed on a side thereof, the first conductive type semiconductor layer is partially exposed through the groove, the insulation layer includes an opening through which the exposed first conductive type semiconductor layer is at least partially exposed, the first electrode extension includes extension contact portions in contact with the first conductive type semiconductor layer through an opening, and the second electrode extension includes an end with a width different from the average width of the second electrode extension.

Abstract: A display device and a chip-on-film structure thereof are provided. The chip-on-film structure includes a substrate, multiple first output pads, multiple second output pads, multiple first lead wires, and multiple second lead wires. The substrate has a surface including a bonding zone. The first and output pads are located in the bonding zone. The first lead wires and the first output pads are located on the same surface of the substrate. The first lead wires and the second lead wires are located on two opposite surfaces of the substrate. Each of the first lead wires is connected to one of the first output pads. Each of the second lead wires is connected to one of the second output pads. The second lead wires each have a portion corresponding to the bonding zone and having the terminal sections that are respectively opposite to the first and second output pads.

Abstract: A pixel of an organic light emitting display device includes a driving thin film transistor (TFT) on a substrate, a switching TFT on the substrate, and an organic light emitting diode (OLED) on the substrate. The driving TFT includes a first active layer including poly-Si, a first insulation layer on the first active layer, and a first source electrode and a first drain electrode contacting the first active layer. At least a portion of the first source electrode and at least a portion of the first drain electrode are disposed on different layers. The switching TFT is electrically connected to the driving TFT, and the switching TFT includes a second active layer including oxide semiconductor material. The OLED is electrically connected to the driving TFT.

Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.

Abstract: A scribe line structure including a semiconductor substrate, a pad and a first patterned metal layer is provided. The semiconductor substrate has a die region, a die sealing region located outside the die region and a dicing region located outside the die sealing region. The pad is disposed in the dicing region. The first patterned metal layer is disposed in the dicing region, right below and connected to the pad, wherein the first patterned metal layer has a plurality of first patterns directly connected to each other.

Abstract: A power device includes an active area having at least two switchable regions with different threshold voltages.

Abstract: An electronic component includes: a plurality of first substrates that are connected in series along a coupling path; and a second substrate that is connected with one first substrate of the plurality of first substrates. The second substrate is in line with the one first substrate along a connection direction intersecting the coupling path, and the plurality of first substrates and the second substrate are configured to be foldable such that they are stacked.

Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies having a stiffener that extends beyond a package substrate outer edge, computing devices incorporating the IC package assemblies, methods for formation of the IC package assemblies, and associated configurations. An IC package assembly may include a package substrate having a first side, a second side opposite the first side, and an outer edge extending between the first side and the second side; an IC die coupled with the first side of the package substrate, where the IC die includes a power terminal; a stiffener coupled with the first side of the package substrate, where the stiffener surrounds the IC die and includes a conductive routing region coupled with the IC die power terminal, and a passive electronic device coupled with the conductive routing region. Other embodiments may be described and/or claimed.

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: The various embodiments described herein include methods, devices, and systems for fabricating and operating transistors. In one aspect, a transistor includes: (1) a semiconducting component configured to operate in an on state at temperatures above a semiconducting threshold temperature; and (2) a superconducting component configured to operate in a superconducting state while: (a) a temperature of the superconducting component is below a superconducting threshold temperature; and (b) a first current supplied to the superconducting component is below a current threshold; where: (i) the semiconducting component is located adjacent to the superconducting component; and (ii) in response to a first input voltage, the semiconducting component is configured to generate an electromagnetic field sufficient to lower the current threshold such that the first current exceeds the lowered current threshold, thereby transitioning the superconducting component to a non-superconducting state.

Abstract: The present invention relates to a composition for a display sealing material having a photopolymerization initiator and a photocurable monomer, the photocurable monomer comprising: a monomer not having the aromatic hydrocarbon group; and a monomer having two or more substituted or unsubstituted phenyl groups of chemical formula 1, wherein about 5 wt % to about 45 wt % of the monomer having two or more substituted or unsubstituted phenyl groups is comprised on the basis of the photocurable monomer and about 55 wt % to about 95 wt % of the monomer not having the aromatic hydrocarbon group is comprised on the basis of the photocurable monomer.

Abstract: An optoelectronic semiconductor device comprises a substrate; a semiconductor system including a first conductivity layer and a second conductivity layer, wherein the second conductivity layer comprises a top surface, and in a top view of the semiconductor system, an outline of the first conductivity layer surrounds an outline of the second conductivity layer; a first electrical connector on the first conductivity layer; a second electrical connector comprising a top view shape and directly contacting the second conductivity layer; a contact layer contacting the top surface of the second conductivity layer and having an outer perimeter at an inner side of the outline of the second conductivity layer in the top view of the semiconductor system; and a discontinuous region contacting the top surface of the second conductivity layer, wherein the contact layer covers a top surface and sidewalls of the discontinuous region.

Abstract: A dispersion comprised of at least 49 wt % of additive particles, a polymerizable monomer, a dispersant and a solvent. Upon polymerization the dispersion forms a hard coat with a haze of at most 0.5% and a transmission of at least 90%. A hard coat comprises at least 49 wt % of additive particles dispersed in a polymer. A method of making a hard coat comprises forming a dispersion, applying the dispersion to one side of a substrate, and polymerizing the dispersion. The hard coat has a haze of at most 0.5% and a transmission of at least 90%.

Abstract: The disclosure provides a method for manufacturing a flexible display device and a flexible display device. The manufacturing method comprises: providing a bottom film to be treated, the bottom film being divided into a bezel bending area and a remaining area; surface treating the upper surface of the bottom film, such that an adhesive force between the bezel bending area and an adhesive layer to be laminated is less than an adhesive force between the remaining area and the adhesive layer to be laminated; providing a display panel to be laminated, and adhering the display panel to the upper surface of the bottom film via the adhesive layer; removing a portion of the bottom film that is located within the bezel bending area.

Abstract: Embodiments described herein generally relate methods for selective deposition of carbon structures. In one embodiment, a method includes forming energized carbon species in a process chamber, diffusing the energized carbon species through a metal layer, wherein the metal layer is disposed on a first surface of a first material that is coplanar with a second surface of a second material, and forming a carbon structure between the first surface of the first material and the metal layer from the energized carbon species. Because the carbon structure is selectively deposited on the first surface and self-aligned to the first material, the possibility of overlay or misalignment of subsequent device layers formed on the first surface of the first material after the removal of the carbon structure is significantly reduced.

Abstract: A semiconductor device according to one embodiment includes a semiconductor substrate having a first surface, an insulating isolation film disposed at the first surface, and a gate electrode. The semiconductor substrate has a source region, a drain region, a drift region, and a body region. The insulating isolation film has a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion. The gate electrode faces a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion. The gate electrode is disposed so as to extend over the second portion and the third portion.

Abstract: The present disclosure generally relates to methods and apparatus for heating a substrate as well as a slot management method for a thermal treatment chamber that in one embodiment includes providing a first substrate to a first slot of a carrier in the thermal treatment chamber via a transfer opening formed in the thermal treatment chamber, the first substrate having a specified anneal time, heating the substrate, moving the carrier to a lowermost position in the thermal treatment chamber using an elevator mechanism coupled to the carrier, and moving the carrier such that the first slot is in a position adjacent to the transfer opening using the elevator mechanism within a carrier transfer time period and transferring the first substrate out of the thermal treatment chamber at a determined time period for anneal.

Abstract: A device includes multiple ceramic capacitors and a current path structure. A first ceramic capacitor includes a first ceramic material between first and second electrodes. A second ceramic capacitor includes a second ceramic material between third and fourth electrodes. The second ceramic material has a higher Q than the first ceramic material. The current path structure includes a lateral conductor located between the first and second ceramic materials, and first and second vertical conductors that extend from first and second ends of the lateral conductor to a device surface. The device may be coupled to a substrate of a packaged RF amplifier device, which also includes a transistor. For example, the device may form a portion of an output impedance matching circuit coupled between a current carrying terminal of the transistor and an output lead of the RF amplifier device.

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.