Abstract: In accordance with a specific embodiment of the present invention one of a first, second, and third reference signal generator is selected. When a first reference signal generator is selected, a value associated with the pulse width modulated register is compared to a second register to control generation of the reference clock. When a second reference signal generator is selected, a phase accumulator is used to generate the reference clock. When a third reference signal generator is selected, a digital phase locked loop generates the reference clock. The present invention is better understood with reference to specific embodiments.

Abstract: The present invention provides a system, method and an apparatus for a digital video decoder, which includes a data processor that utilizes at least an encoded video data stream to produce one or more output streams. The one or more output streams includes at least a set of motion compensation instructions.