Abstract: A word processor with a main body having a keyboard and a liquid crystal display panel for making a display thereon according to a key operation on the keyboard also includes a lighting unit which is detachably attachable to the main body near the display panel. The lighting unit includes a box-shaped case having an openable lid, a light source disposed inside this case, a mirror attached to the lid so as to reflect light from the light source and to thereby illuminate the display panel when the lid is opened, and terminals which automatically become connected to a power source as the lighting unit is attached to the main body.

Abstract: A machine translation system capable of obtaining a consistent translation for an entire document by taking context into account in translating each word or sentence. In this system, document information necessary to remove uncertainty in the translation due to a presence of a plurality of candidates for the translation is utilized whenever uncertainity due to a presence of a plurality of candidates for the translation arises by attempting to translate according to a translation dictionary containing rules for translation.

Abstract: An improved device driver for a real time computer system operated by a nonmultitasking operation system and controlling the operation of polled peripheral devices which do not have an interrupt generation capability. The improved device driver of the present invention operates on the general principle of releasing control back to the operating system before completion of a task when a peripheral device is not in a state of readiness to perform its task. The technical approach is a single entry software routine utilizing a state variable to keep track of the internal state of execution of the device driver, which relinquishes control back to the operating system while waiting for the device to become ready to respond, thus allowing the CPU to execute other tasks.

Abstract: A processor interconnect network (PIN) for operating a printing press having a plurality of different modules each containing a processor. The PIN has: a control for communicating having a plurality of ports connected to the plurality of processors in the modules of the printing press in a one-to-one correspondence and each of the modules being equivalent to a node in a local area network and having a unique address. In the processor interconnect network the control and the plurality of modules form substantially a star network. Addition modules can be connected to unused available ports of the control without substantial change to opeating the star network.

Abstract: A cache management system for a computer system having a central processing unit, a main memory, and cache memory including a memory management unit for transferring page size blocks of information, apparatus for reading information from main memory, apparatus for writing information to the cache memory, and apparatus for overlapping the write of information to the cache memory to occur during the read of information from the main memory.

Abstract: A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

Abstract: Individual training stations are able to record and play back a student's own pronunciations as well as to reproduce the recorded pronunciations of the fellow students and of prerecorded voice teaching aids by means of a digital memory and controller.

Abstract: A data processing system having a dual arbiter for controlling access to a system bus where two processors, each clocked by one of two timing signals having equal periods but out of phase by half a period, operate synchronously each to the other, but outphased by the half period of the clock signal, and generate equal priority signals requesting access to a system bus, each processor in a time distinct and non overlapped phase of the respective timing signals, and where an arbitration unit grants system bus access to either one or the other requesting processor on the time order in which the access requesting signals are received, the granting being performed asynchronously and without sampling and set up delays.