Abstract: A flattened layer (6) formed between a micro-condenser lens (7) and an Al light-shielding layer (5) is formed as a bilayer and this bilayer is formed by sequentially laminating a first layer (6a) and a second layer (6b) having a refractive index (N.sub.2) lower than a refractive index (N.sub.1) of the first layer (6a). Therefore, of the incident light converged by the micro-condenser lens (7), a light component shielded by the shoulder portion of the Al light-shielding layer (5) is reduced and a sensitivity increasing effect, which is an effect inherent in the condenser lens, can be demonstrated sufficiently, which can make the CCD solid state imager compact in size and which can improve the image quality.

Abstract: A high current amplifier, three terminal device, comprising a Josephson tunnel junction and a Schottky diode is configured so that the Josephson junction and Schottky diode share a common base electrode which is made very thin. Electrons which cross the Schottky barrier are supplied to the Josephson junction to obtain the amplified output current.

Abstract: An optoelectronic device with a very low series resistance has a III-V substrate, a lower, n-doped III-V material semiconducting confinement layer placed on the substrate, an active zone having at least one active, not intentionally doped III-V material semiconducting layer placed on the lower confinement layer, an upper, p-doped III-V material semiconducting confinement layer covering said active zone, the forbidden energy band of the active layer being lower than that of the confinement layers. Two metal coatings are placed on two opposite faces of the device and there is a highly n-doped, quaternary III-V material semiconducting layer for stopping the diffusion of doping ions from the upper confinement layer and placed between the active layer and the upper confinement layer, said stopping layer having a thickness smaller than that of the active layer and also forming part of the active zone.

Abstract: The thickness of a DI island structure is reduced and the performance of bipolar and JFET structures enhanced by shaping the bottom of the DI island during anisotropic etching to define isolated islands, so that the resulting structure contains one or more projections whose separation from the topside diffusion predefines operational characteristics of the device. If the projection is directly beneath the bottom of a gate diffusion, pinch-off voltage of a JFET device is reduced without substantially affecting channel resistance. When the projection is positioned so that its inclined surface extends alongside the curvilinear PN junction formed between the gate diffusion and the island, channel thickness and sensitivity of channel thickness to viriations in island thickness are reduced.

Abstract: An electrode assembly for a semiconductor device includes a contact layer formed on a semiconductor substrate and consisting mainly of a rare-earth metal or metals, or a silicide thereof, or a mixture thereof, and a diffusion barrier layer formed on the contact layer and consisting mainly of iron or an iron alloy. The assembly is bonded to a mount by a solder layer formed on the diffusion barrier layer and consisting mainly of lead and tin.

Abstract: A non-linear superconducting junction device comprising a layer of high transient temperature superconducting material which is superconducting at an operating temperature, a layer of metal in contact with the layer of high temperature superconducting material and which remains non-superconducting at the operating temperature, and a metal material which is superconducting at the operating temperature and which forms distributed Sharvin point contacts with the metal layer.

Abstract: The present invention is a CMOS epitaxial silicon wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped monocrystalline silicon substrate (56) having a major surface (54) that supports a lightly doped monocrystalline epitaxial silicon layer (52). The substrate includes a heavily doped diffused layer (58) extending a short distance (64) into the substrate from the major surface toward a lightly doped bulk portion (66) of the substrate. CMOS integrated circuits manufactured on the epitaxial layer of the CMOS wafer of this invention have a low susceptibility to latch-up. The low susceptibility is provided by the relatively low resistivity of the diffused layer. Since the diffused layer is relatively thin and the bulk portion is lightly doped, the oxygen content of the bulk can be readily measured and controlled.

Abstract: A semiconductor integrated circuit is provided which can have a high holding current without the penalty of a high gate current. Such a circuit includes a PNPN device and junction bipolar transistor in which a further doped region of the same conductivity type as the transistor collector region and more heavily doped than the collector region prevents the devices affecting each other. The junction bipolar transistor has a current gain of at least 10 and base-collector and base-emitter junctions with reverse breakdown voltages of at least 50 volts. A PN diode can also be used in the circuit.

Abstract: A temperature sensor is monolithically integrated in a semiconductor body together with a vertical power semiconductor structure. The power semiconductor structure is formed of a plurality of power cells. The temperature sensor is formed of two sensor cells that can be manufactured simultaneously with the power cells. The advantage of the invention is that a highly sensitive temperature sensor can be manufactured in process-compatible fashion together with a vertical power semiconductor structure without additional steps and in a cost-beneficial way.

Abstract: In the prior art, selective epitaxial growth (SEG) of semiconductors, performed typically in rectangular windows penetrating through a masking layer located on a major surface of semiconductor substrate, suffers from unwanted facet formation at the corners of the windows--whereby the desirable planar area available for transistor fabrication is reduced. Such facet formation is suppressed--i.e., the area occupied by unwanted facets is reduced--by adding a relatively small lobe penetrating through the masking layer at each corner of each window prior to performing the SEG, whereby transistor packing density can be increased.

Abstract: The present invention is directed to a high voltage field effect transistor (FET) constructed on the major surface of a substrate of a first conductivity type. The FET includes a drain region of a second conductivity type located in the major surface and a generally annular drift region of the second conductivity type, located in the major surface and outside of the drain region. A generally annular gate is located on the major surface and outside of the drift region, and a generally annular source region is located in the major surface and outside of the gate. A first channel stop is located in the major surface and outboard of the source region, and a second channel stop located in the major surface and beneath the gate, having at least two portions in close proximity to each other. A channel region is located in the major surface and between the two second channel stop portions. The second channel stop blocks communication between the source region and the drift region except through the channel region.

Abstract: A HEMT type semiconductor device includes a semiconductor substrate, a buffer semiconductor layer formed on the substrate, a first semiconductor well layer formed on the buffer layer and serving as a first conductivity type channel layer, a second semiconductor well layer formed on the first well layer and serving as a second conductivity type opposite the first conductivity, a channel layer and a potential barrier layer formed on the second well layer and forming a potential barrier for carriers. The substrate is made of GaAs or InP, and the layers are successively and epitaxially grown on the substrate. A two dimensional hole gas and a two dimensional electron gas are confined in the first well layer and in the second well layer, respectively.

Abstract: A field effect transistor is formed on a side surface of an elevation protruded from the upper surface of a substrate. A gate electrode is formed on the side surface with a gate insulating film therebetween. Source and drain regions are formed in the top of the elevation and the surface of the substrate adjacent to the elevation by ion implantation with the gate electrodes as a mask.

Abstract: Disclosed herein is a diamond Schottky gate type field effect transistor (FET) comprising: an insulating diamond under layer; a doped semiconducting diamond layer as an active layer, which has electrode areas formed by ion implantation such that the interface level is formed near the surface thereof; an insulating diamond layer formed on a portion of the semiconducting diamond layer; a source electrode made of a degenerate diamond film provided in one of the electrode areas of the semiconducting diamond layer, to form an ohmic contact between the same and the semiconducting diamond layer; a drain electrode made of a degenerate diamond film provided in the other of the electrode areas of the semiconducting diamond layer, to form an ohmic contact between the same and the semiconducting diamond layer; and a gate electrode made of a degenerate diamond film formed on the insulating diamond layer, to form a Schottky junction between the same and the semiconducting diamond layer through the diamond insulating layer.

Abstract: A method is provided for writing into a semiconductor memory which includes a MOS transistor formed on a semiconductor substrate and an anti-fuse formed of an insulating film and an upper electrode on a drain of the MOS transistor. The method includes the steps of applying a first voltage between the upper electrode of the anti-fuse and a source of the MOS transistor to cause dielectric breakdown of the insulating film of the anti-fuse, with the MOS transistor turned on; and applying a second voltage between the upper electrode of the anti-fuse and the semiconductor substrate so that a larger amount of current flows than the amount of current required for breaking down the insulating film of the anti-fuse.

Abstract: A power switching metal oxide semiconductor (PSMOS) transistor comprises a plurality of vertical double-diffused MOS (VDMOS) transistors formed on a semiconductive substrate of a first type conductivity and a device for bypassing avalanche carriers generated at the time of turning OFF the vertical double-diffused MOS transistors. The bypass device includes a first semiconductive region, which is spaced from the MOS transistor, of a second type conductivity formed on the semiconductor substrate and a conductive line for connecting the first semiconductive region to a source electrode of the MOS transistor.

Abstract: A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.

Abstract: A semiconductor device having a moisture barrier comprises a semiconductor substrate, a plurality of bonding pads arranged along at least one side of the semiconductor substrate, and an insulating film provided between at least one side of the semiconductor substrate and the bonding pads opposite to that side, and provided with means for preventing incursion of moisture, thereby to prevent moisture from being absorbed from the chip side surface. Further, there is also disclosed a method of manufacturing such a semiconductor device, which comprises the steps of forming an insulating film on a semiconductor wafer, forming a plurality of bonding pads arranged along dicing lines of the semiconductor wafer, and forming a contact hole or a via hole in the insulating film, and forming at the same time, a groove structure so that it is arranged between the dicing lines and the plurality of bonding pads.

Abstract: A molded device package supports a volatile memory chip and a replaceable backup battery for preserving data in the event of loss of main power supply. The package includes an external socket for receiving a replaceable backup battery which can be manually inserted into or removed from the socket after molding encapsulation and metal trim work have been completed. The socket is intersected by an exposure cavity which permits the positive and negative terminals of a backup battery to engage positive and negative finger leads. The positive and negative battery terminals are engaged by resilient terminal contact portions of the positive and negative finger leads which project into the exposure cavity. Socket shoulder portions and a retainer cap hold a backup battery within the socket and in electrical contact with the resilient terminal contact portions.

Abstract: A multi-level wiring structure interconnects circuit components of an integrated circuit fabricated on a semiconductor substrate, and comprises a lower wiring of noble metal covered with an inter-level insulating film, an upper wiring of noble metal extending over the inter-level insulating film, and an inter-level wiring implemented by a tube-shaped metal film filled with a piece of noble metal and passing through the inter-level insulating film for interconnecting the lower and upper wirings so that an electric signal is propagated at high speed without sacrifice of resistivity against migration phenomena.