Abstract: A semiconductor device includes a p-type SiC layer, a gate electrode, and a gate insulating layer between the SiC layer and the gate electrode. The gate insulating layer includes first and second layers and first and second regions. The second layer is between the first layer and the gate electrode and has a higher oxygen density than the first layer. The first region is across the first layer and the second layer, and includes at least one first element selected from the group consisting of N (nitrogen), P (phosphorus), As (arsenic), Sb (antimony), and Bi (bismuth) and the first region having a first concentration peak of the at least one first element. The second region is provided in the first layer, includes a second element from Ta (tantalum), Nb (niobium), and V (vanadium) and, the second region having a second concentration peak of the at least one second element.

Abstract: A semiconductor package includes a plurality of metal leads and a semiconductor die attached to the plurality of metal leads by an interconnect. A surface of the plurality of metal leads, a metallized surface of the semiconductor die, and/or a surface of the interconnect comprises Cu and has a thermal conductivity in a range of 340 to 400 W/mK and an electrical conductivity in a range of 80 to 110% IACS. One or more of the surfaces which comprise Cu and have a thermal conductivity in the range of 340 to 400 W/mK and an electrical conductivity in the range of 80 to 110% IACS also includes micropores having a diameter in a range of 1 ?m to 10 ?m. A method of manufacturing a metal surface with such micropores also is described.

Abstract: A method of fabricating a memory device may include forming a first conductive line extending over a substrate in a first direction, forming a memory cell pillar on the first conductive line, and forming a second conductive line extending over the memory cell pillar in a second direction that intersects the first direction, such that the first and second conductive lines vertically overlap with the memory cell pillar interposed between the first and second conductive lines. The memory cell pillar may include a heating electrode layer and a resistive memory layer. The resistive memory layer may include a wedge memory portion and a body memory portion. The wedge memory portion may contact the heating electrode layer and may have a width that that changes with increasing distance from the heating electrode layer. The body memory portion may be connected to the wedge memory portion.

Abstract: A method for fabricating an electronic package includes providing a metal member including a supporting plate and a plurality of conductive pillars disposed on the supporting plate. A circuit structure is coupled to the conductive pillars. An electronic component is disposed on the metal member and electrically connected to the circuit structure. An encapsulant encapsulates the conductive pillars and the electronic component. Subsequently, the supporting plate is removed. Any mold can be used for fabricating the electronic package, no matter what the size of the electronic package is. Therefore, the fabricating cost of the electronic package is reduced.

Abstract: A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

Abstract: A highly reliable light-emitting device is provided. Damage to an element due to externally applied physical power is suppressed. Alternatively, in a process of pressure-bonding of an FPC, damage to a resin and a wiring which are in contact with a flexible substrate due to heat is suppressed. A neutral plane at which stress-strain is not generated when a flexible light-emitting device including an organic EL element is deformed, is positioned in the vicinity of a transistor and the organic EL element. Alternatively, the hardness of the outermost surface of a light-emitting device is high. Alternatively, a substrate having a coefficient of thermal expansion of 10 ppm/K or lower is used as a substrate that overlaps with a terminal portion connected to an FPC.

Abstract: A method includes: forming first and second trenches in a semiconductor body; forming a first material layer on the semiconductor body in the first and second trenches such that a first residual trench remains in the first trench and a second residual trench remains in the second trench; removing the first material from the second trench; and forming a second material layer on the first material layer in the first residual trench and on the semiconductor body in the second trench. The first material layer includes dopants of a first doping type and the second material layer includes dopants of a second doping type. The method further includes diffusing dopants from the first material layer in the first trench into the semiconductor body to form a first doped region, and from the second material layer in the second trench into the semiconductor body to form a second doped region.

Abstract: A method for producing a micromechanical element includes producing a micromechanical structure, the micromechanical structure having: a functional layer for a micromechanical element, a sacrifical layer at least partly surrounding the functional layer, and a closure cap on the sacrifical layer. The method further includes applying a cover layer on the micromechanical structure. The method further includes producing a grid structure in the cover layer. The method further includes producing a cavity below the grid structure, as access to the sacrifical layer. The method further includes at least partly removing the sacrifical layer. The method further includes applying a closure layer at least on the grid structure of the cover layer for the purpose of closing the access to the cavity.

Abstract: A semiconductor structure is provided that contains a non-volatile battery which controls gate bias and has increased output voltage retention and voltage resolution. The semiconductor structure may include a semiconductor substrate including at least one channel region that is positioned between source/drain regions. A gate dielectric material is located on the channel region of the semiconductor substrate. A battery stack is located on the gate dielectric material. The battery stack includes, a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located on the cathode material, an electrolyte located on the first ion diffusion barrier material, a second ion diffusion barrier material located on the electrolyte, an anode region located on the second ion diffusion barrier material, and an anode current collector located on the anode region.

Abstract: A semiconductor structure includes a substrate having an active region and an isolation region, an insulating layer disposed on the substrate, a seed layer disposed on the insulating layer, a compound semiconductor layer disposed on the seed layer, a gate structure in the active region disposed on the compound semiconductor layer, an isolation structure in the isolation region disposed on the substrate, a pair of through-substrate vias in the isolation region disposed on the opposite sides of the gate structure, and a source structure and a drain structure disposed on the substrate and on the opposite sides of the gate structure. The pair of through-substrate vias pass through the isolation structure and contact the seed layer. The source structure and the drain structure electrically connect the seed layer by the pair of through-substrate vias.

Abstract: A method includes forming a transistor having source and drain regions. The following are formed on the source/drain region: a first via, a first metal layer extending along a first direction on the first via, a second via overlapping the first via on the first metal layer, and a second metal extending along a second direction different from the first direction on the second via; and the following are formed on the drain/source region: a third via, a third metal layer on the third via, a fourth via overlapping the third via over the third metal layer, and a controlled device at a same height level as the second metal layer on the third metal layer.

Abstract: Provided are a display panel and a display device. The display panel includes: a substrate and pixel units provided on the substrate, and the pixel units of at least two different colors are adjacently arranged. In a direction facing away from the substrate, one of the pixel units includes a reflective electrode, a light emitting unit and a color resist, and the light emitting unit and the color resist disposed in a same pixel unit have a same color, a vertical projection of a geometric center of the light emitting unit on the substrate is not overlapped with that of a geometric center of the color resist in the same pixel unit on the substrate. A vertical projection of the color resist in the pixel unit on the substrate is overlapped with that of the light emitting unit in a pixel unit closest to the pixel unit on the substrate.

Abstract: An integrated circuit for a flash memory device with enlarged spacing between select and memory gate structures is provided. The enlarged spacing is obtained by forming corner recesses at the select gate structure so that a top surface with a reduced dimension of the select gate structure is obtained. In one example, a semiconductor substrate having memory cell devices formed thereon, the memory cell devices include a semiconductor substrate having memory cell devices formed thereon, the memory cell devices includes a plurality of select gate structures and a plurality of memory gate structures formed adjacent to the plurality of select gate structures, wherein at least one of the plurality of select gate structures have a corner recess formed below a top surface of the at least one of the plurality of select gate structures.

Abstract: A semiconductor structure includes a semiconductor substrate; a first pad and a second pad on a top surface of the semiconductor substrate; a circuit board including a polymeric pad and an active pad corresponding to the first pad and the second pad on the top surface of the semiconductor substrate respectively; a first bump disposed between the polymeric pad and the first pad; and a second bump disposed between the active pad and the second pad; wherein a first thickness of the polymeric pad is greater than a second thickness of the active pad. Further, a method of manufacturing the semiconductor structure is disclosed. The method includes providing a circuit board; and forming a polymeric pad and an active pad on a surface of the circuit board, wherein a first thickness of the polymeric pad is substantially greater than a second thickness of the active pad.

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

Abstract: A vertical memory device includes a substrate having a trench structure, gate electrodes on the substrate, the gate electrodes being spaced apart from each other in a first direction substantially vertical to an upper surface of the substrate, a channel including a vertical portion extending through the gate electrodes in the first direction, and a horizontal portion extending in the trench structure in a second direction substantially parallel to the upper surface of the substrate, the horizontal portion being connected the vertical portion, and an epitaxial layer on a first portion of the substrate and connected to the horizontal portion of the channel, the first portion of the substrate being adjacent to ends of the gate electrode in the second direction.

Abstract: The semiconductor device has a wiring M 2, an interlayer insulating film IL3 formed on the wiring M 2, and two wirings M 3 formed on the interlayer insulating film IL3, and the wiring M 3 is connected to the wiring M 2 by a conductor layer PG2 formed in the interlayer insulating film IL3. A recess CC3 is formed on the upper surface IL3a of the interlayer insulating film IL3, and the recess CC3 is defined by a side surface S 31 connected to the upper surface IL3a and a side surface S 32 connected to the side surface S 31, and the side surface S 32 is inclined so that the width WC3 of the recess CC3 decreases in the direction from the upper surface IL3a of the interlayer insulating film IL3 toward the upper surface IL2a of the interlayer insulating film IL2.

Abstract: Method for fabricating an insulated gate bipolar transistor (IGBT) is provided. A substrate includes a device region, that includes control regions and turn-off regions, arranged alternately. A drift region is formed in the substrate. A well region is formed in a portion of the substrate in the control regions and the turn-off regions, and first gate structures are formed in the control regions. The well region is in contact with the drift region, and the first gate structures are in contact with both the drift region and the well region. Emission regions are formed in the well region of the control regions and in the substrate on one or both sides of each first gate structure, the drift region and each emission region are separated by the well region, and the emission regions are electrically connected to a portion of the well region in the turn-off region.

Abstract: A resistive random-access memory device formed on a semiconductor substrate includes a first interlayer dielectric formed over the semiconductor substrate and includes a first via. A chemical-mechanical-polishing stop layer is formed over the interlayer dielectric. A lower metal layer formed in the first via has a top surface extending above a top surface of the chemical-mechanical-polishing stop layer. A dielectric layer is formed over the chemical-mechanical-polishing stop layer and is in electrical contact with the lower metal layer. A barrier metal layer is formed over the dielectric layer. Edges of the dielectric layer and the first barrier metal layer extend beyond outer edges of the first via. A second interlayer dielectric layer including a second via is formed over the dielectric layer. An upper metal layer formed in the second via in electrical contact with the barrier metal layer.

Abstract: Inter-die passive interconnects are lengthened while locating I/O circuitry away from die edge, such that passive interconnect length is agglomerated toward the die edge, and inter-die communication is expedited.