Abstract: A method is provided for area-selective deposition on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a target surface of a first material an non-target surface of a second material different than the first material is received into the platform. An additive material is selectively deposited on the workpiece with the additive material forming on the target surface at a higher deposition rate than on the non-target surface, followed by etching to expose the non-target surface. The integrated sequence of processing steps is executed within the platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.

Abstract: An image forming apparatus includes: a board; a semiconductor integrated circuit that is provided on the board and has a real-time clock circuit; a radiator that is provided at a position for covering the semiconductor integrated circuit and receives heat from the semiconductor integrated circuit and radiates the heat; and an oscillator that is provided in a space sandwiched between the board and the radiator and vibrates to supply a clock signal to the real-time clock circuit.

Abstract: Disclosed herein are approaches to fabricating solar cells, solar cell strings and solar modules using roll-to-roll foil-based metallization approaches. Methods disclosed herein can comprise the steps of providing at least one solar cell wafer on a first roll unit and conveying a metal foil to the first roll unit. The metal foil can be coupled to the solar cell wafer on the first roll unit to produce a unified pairing of the metal foil and the solar cell wafer. We disclose solar energy collection devices and manufacturing methods thereof enabling reduction of manufacturing costs due to simplification of the manufacturing process by a high throughput foil metallization process.

Abstract: A method for screen printing, including: by using a screen printing apparatus provided with a screen printing plate having an opening part corresponding to a printing pattern, a scraper, and a squeegee, filling a paste supplied on an upper surface of the screen printing plate into the opening part of the screen printing plate by the scraper; and, after that, pushing out the paste to a predetermined position of an object to be printed from the opening part of the screen printing plate by the squeegee to screen-print the paste corresponding to the printing pattern on the object to be printed, wherein the humidity in the screen printing apparatus is adjusted during the screen printing. As a result, by controlling an amount of moisture in the paste on the screen printing plate, a screen printing method is capable of improving the printing property of the paste.

Abstract: A power module includes a base plate, a ceramic insulating substrate bonded on the base plate, and a semiconductor element bonded on the ceramic insulating substrate, wherein a surface of the base plate on a side opposite to the ceramic insulating substrate has a warp with a convex shape, and a linear thermal expansion coefficient ?1 (×10?6/K) of the base plate and a linear thermal expansion coefficient ?2 (×10?6/K) of the ceramic insulating substrate when a temperature decreases in the range of 25° C. to 150° C. satisfy the following Expression (1).

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: A semiconductor device includes: a first electrode terminal; a second electrode terminal; a semiconductor element having an electrode on one surface connected to one surface of the first electrode terminal; a wire that connects an electrode on the other surface of the semiconductor element and the second electrode terminal; and a resin portion formed of an insulator covering the semiconductor element, a part of the second electrode terminal, and the one surface of the first electrode terminal, wherein a chamfered portion is formed on at least one of end portions where the first electrode terminal and the second electrode terminal face each other.

Abstract: A method of manufacturing a via hole, a method of manufacturing an array substrate and an array substrate are provided. The method of manufacturing an via hole includes: providing a base substrate; forming an insulation layer on the base substrate; etching the insulation layer by using a first etching process to forma groove in the insulation layer; performing an ion implantation process with ions on a portion of the insulation layer exposed by the groove to form an ion implantation region; and etching a portion of the insulation layer in the ion implantation region by using a second etching process to form a via hole penetrating the insulation layer.

Abstract: Described herein is a technique capable of providing a semiconductor device having good characteristics. According to the technique described herein, there is provided a method of manufacturing a semiconductor device, including: (a) loading a substrate into a process chamber; and (b) forming a stacked etch stopper film by performing: (b-1) forming a first etch stopper film containing a first element and a second element by supplying a first element-containing gas and a second element-containing gas onto the substrate; and (b-2) forming a second etch stopper film containing the first element, the second element and a third element by supplying the first element-containing gas, the second element-containing gas and a third element-containing gas onto the first etch stopper film.

Abstract: A polishing unit 3A includes a state acquisition section 846 and a learning section. The state acquisition section can acquire a state variable including at least one of data on a state of a top ring making up the polishing unit and data on a state of a semiconductor wafer. The learning section has learned a relationship between the state variable and a change in film thickness of the semiconductor wafer using a neural network, the learning section being capable of receiving the state variable from the state acquisition section to predict the change and/or receiving the state variable from the state acquisition section to determine that the change is abnormal.

Abstract: According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a plurality of electrode layers and a plurality of insulating layers. Each of the insulating layers is provided between the electrode layers. The first intermediate layer is provided between the stacked units. The first intermediate layer is made of a material different from the electrode layers and the insulating layers. The plurality of columnar portions includes a channel body extending in a stacking direction of the stacked body to pierce the stacked body, and a charge storage film provided between the channel body and the electrode layers.

Abstract: The invention relates to a method for creating a detachment zone (2) in a solid (1) in order to detach a solid portion (12), especially a solid layer (12), from the solid (1), said solid portion (12) that is to be detached being thinner than the solid from which the solid portion (12) has been removed.

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures.

Abstract: A method of cleaning a contact hole of a semiconductor device, can include: removing a first portion of an object to be removed in the contact hole by a dry cleaning process, where a second portion of the object to be removed remains after the dry cleaning process has completed; and removing the second portion of the object to be removed by a wet cleaning process. The method can further include: forming an interlayer dielectric layer on a semiconductor substrate having a contact region; etching the interlayer dielectric layer to form the contact hole, where the contact hole penetrates the interlayer dielectric layer and exposes the contact region; and after the cleaning of the contact hole, filling the contact hole by a metal material to form a metal plug that is in contact with the contact region.

Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

Abstract: A semiconductor package includes a package main body. The package main body includes: a lead frame that includes first terminals and a die pad; two or more integrated circuit chips that are disposed on the die pad; one or more electrically conductive members that are disposed on the die pad; wires that connect the first terminals and the integrated circuit chips electrically; and a molded member that seals the lead frame, the integrated circuit chips, the electrically conductive member, and the wires. An upper surface, a bottom surface, and side surfaces of the package main body are formed by the molded member. The electrically conductive member is exposed through the upper surface of the package main body, and the die pad is exposed through the bottom surface of the package main body.

Abstract: A method is provided for gate contact formation on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform (CMP) hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a contact feature formed therein, and inspected throughout, the contact feature having a semiconductor contact surface exposed, is received into the CMP. A plurality of metal layers is deposited at a bottom of the contact feature after the workpiece is treated to remove contamination. The integrated sequence of processing steps is executed within the CMP without leaving the controlled environment, the transfer modules used to transfer the workpiece between the modules while maintaining the workpiece within the controlled environment.

Abstract: According to one embodiment, a radiation detector includes a detection element. The detection element includes a first conductive layer, a second conductive layer, and an organic semiconductor layer provided between the first conductive layer and the second conductive layer. The organic semiconductor layer includes a first compound and a second compound. The first compound is bipolar. A thickness of the organic semiconductor layer is 50 ?m or more.

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

Abstract: A method of forming an oxide layer, the method including forming a first material layer on a semiconductor substrate, the first material layer including a polysiloxane material, wherein, from among Si—H1, Si—H2, and Si—H3 bonds included in the polysiloxane material, a percentage of Si—H2 bonds ranges from about 40% to about 90%, performing a first annealing process on the first material layer in an inert atmosphere, and performing a second annealing process on the first material layer in an oxidative atmosphere.