Abstract: The Facet Navigator permits users to set custom constraints for searching databases by facet, displays facets representing fields in a database, and provides a manipulator for each facet. The manipulator may be a slider bar, or a drop-down menu, or some other interactive device known to persons skilled in the art. When a user sets constraints for a facet with the manipulator, the Facet Navigator searches the database based on the constraints and displays a list of items in the database that satisfy the constraints. The Facet Navigator displays a preview of interim results whenever a cursor is moved over an active region of the manipulator, where the preview includes details of database items meeting a search criteria based on the location of the cursor on the manipulator.

Abstract: A method, device, and system for resetting snapshots are provided. The reset of a snapshot incorporates the traditional snapshot delete and snapshot create operations into a single operation. Additionally, a snapshot created under the reset operation may receive an array partition from a snapshot being deleted under the same snapshot reset operation thereby retaining its identifying characteristics.

Abstract: A system for programming non-volatile storage is proposed that reduces the impact of interference from the boosting of neighbors. Memory cells are divided into two or more groups. In one example, the memory cells are divided into odd and even memory cells; however, other groupings can also be used. Prior to a first trigger, a first group of memory cells are programmed together with a second group of memory cells. Subsequent to the first trigger and prior to a second trigger, the first group of memory cells are programmed separately from the second group of memory cells. Subsequent to the second trigger, the first group of memory cells are programmed together with the second group of memory cells. Before and after both triggers, the first group of memory cells are verified together with the second group of memory cells.

Abstract: A circuit for driving a plurality of light sources via a current generator, wherein the light sources are grouped into a plurality of light source sets wherein the driver circuit comprises a plurality of inductive elements, a plurality of switches adapted to selectively connect each light source set in series with one of the inductive elements, and a control circuit configured for driving the switches, so that during a first operation time interval, each light source set is connected in series with a respective first inductive element, and during a second operation time interval, each light source set is connected in series with a respective second inductive element, wherein the respective second inductive element is separate from the respective first inductive element.

Abstract: A converter for feeding a load via an inductor with a current having a controlled intensity between a maximum level and a minimum level may include: a switch switchable on and off to permit or prevent, respectively, feeding of current towards said inductor; first and second current sensors sensitive to the current flowing through said switch when said switch is on or off, respectively; comparator circuitry to identify if the current intensity detected by said first current sensor and said second current sensor reaches said maximum level and said minimum level, respectively, by generating respective logical signals; and drive circuitry for said switch sensitive to said logical signals and configured to turn off said switch when the current intensity detected by said first sensor reaches said maximum level and turning on said switch when the current intensity detected by said second current sensor reaches said minimum level.

Abstract: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.

Abstract: A system for acquiring an ultrasound signal comprises a signal processing unit adapted for acquiring a received ultrasound signal from an ultrasound transducer having a plurality of elements. The system is adapted to receive ultrasound signals having a frequency of at least 20 megahertz (MHz) with a transducer having a field of view of at least 5.0 millimeters (mm) at a frame rate of at least 20 frames per second (fps). The signal processing can further produce an ultrasound image from the acquired ultrasound signal. The transducer can be a linear array transducer, a phased array transducer, a two-dimensional (2-D) array transducer, or a curved array transducer.

Abstract: The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Abstract: An LED apparatus includes a base having thermal conductivity, an insulative substrate provided on one surface of the base and including electrodes provided on a surface of the substrate, at least one base-mounting area that is an exposed part of the base, exposed within a pass-through hole provided in the substrate, a plurality of LED elements mounted on the base in the base-mounting area and some of the LED elements in a unit electrically connected to the electrodes in series, a plurality of the units are electrically connected in parallel, and a frame disposed to surround the base-mounting area and configured to form a light-emitting area.

Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Abstract: A method is disclosed. The method includes receiving an update package from a wireless service provider that includes information indicating that multiple language versions of an update are included in the update package. Based on the information, the method further specifies an update associated with a language from the update package, and transmits the update associated with the language to a wireless device.

Abstract: A method for using a synchrotron, the method including the steps of: providing a synchrotron designed to accelerate a hadron beam to higher momenta; altering said synchrotron to enable deceleration of hadron beams to lower momenta; and using the synchrotron in said altering step in decelerating a hadron beam to lower momentum.

Abstract: A split bridge circuit for rectifying the alternating current house supply into direct current (D.C.), using hi-polar transistor as rectifying devices. Using specified terminals of the bi-polar transistors results in a high forward voltage drop across the transistors (particularly as compared to the voltage drop across diode rectifiers in the prior art circuits), which reduces ripple significantly and lessens, or even eliminates, the need for a series limiting resistor in the circuit.

Abstract: The present invention addresses the problem of providing illumination in a manner that is energy efficient and intelligent. In particular, the present invention uses distributed processing across a network of illuminators to control the illumination for a given environment. The network controls the illumination level and pattern in response to light, sound, and motion. The network may also be trained according to uploaded software behavior modules, and subsets of the network may be organized into groups for illumination control and maintenance reporting.

Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.

Abstract: An arrangement wherein a plurality of LED strings are driven with a balanced drive signal, i.e. a drive signal wherein the positive side and negative side are of equal energy over time, is provided. In a preferred embodiment, the drive signal is balanced responsive to a capacitor provided between a switching network and a driving transformer. Balance of current between various LED strings is provided by a balancing transformer.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) comprises an isolated forward converter comprising a transformer, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducting through to a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The forward converter comprises a sense resistor coupled in series with the primary winding for producing the sense voltage that is representative of the primary current. The current sense circuit receives the sense voltage and averages the sense voltage when the semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.

Abstract: The present invention provides LEDs and zener diodes that are homo-polar and connected in parallel to constitute the first set of LED and zener diode and a second set of LED and zener diode; the first LED and zener diode set and the second LED and zener diode assume a reverse polarity series connection to constitute the voltage-limiting and reverse polarity series type LED device; through the selection of connecting pins, it is used on direct current power source or alternating current power source which is its characteristics.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.