Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the efficiency in condensing the light by forming a multi-layered micro lens with various materials having different refractive indexes, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate; an insulating interlayer on the plurality of photosensitive devices; a plurality of color filter layers in correspondence with the respective photosensitive devices, to filter the light by respective wavelengths; a first micro-lens layer on an entire surface of the color filter layers, to condense the light; and a plurality of second micro-lens layers on the first micro-lens layer in correspondence with the respective photosensitive devices, wherein the second micro-lens layer has the different refractive index from that of the first micro-lens layer.

Abstract: A semiconductor device has a semiconductor chip, a first insulating film and an inductor. The semiconductor chip includes an integrated circuit formed on the main surface of the chip and a plurality of pad electrodes formed on the main surface of the chip and electrically connected to the integrated circuit. The first insulating film of an insulating resin material is formed on the main surface of the semiconductor chip, covers the integrated circuit, and includes a plurality of contact holes provided on the respective pad electrodes. The inductor is formed on the inductor formation region of the first insulating film, and both terminals of the inductor are connected to the pad electrodes through the contact holes, respectively. The inductor formation region of the first insulating film is formed thicker than a portion of the first insulating film around the contact hole.

Abstract: A dielectric film is formed by atomic layer deposition to conformally fill a narrow, deep trench for device isolation. The method of the illustrated embodiments includes alternately pulsing vapor-phase reactants in a string of cycles, where each cycle deposits no more than about a monolayer of material, capable of completely filling high aspect ratio trenches. Additionally, the trench-fill material composition can be tailored by processes described herein, particularly to match the coefficient of thermal expansion (CTE) to that of the surrounding substrate within which the trench is formed. Mixed phases of mullite and silica have been found to meet the goals of device isolation and matched CTE. The described process includes mixing atomic layer deposition cycles of aluminum oxide and silicon oxide in ratios selected to achieve the desired composition of the isolation material, namely on the order of 30% alumina and 70% silicon oxide by weight.

Abstract: A method for making a multilayer interconnect electronic component structure, and, in particular, an integrated circuit semiconductor device made using a copper damascene method is provided. The process of the invention uses a method for pre-cleaning exposed copper surfaces in the structure. The method employs a cleaning composition containing a nitrogen containing material and an oxygen containing material and also optionally a hydrogen containing material to remove the copper oxide film on copper surfaces in the structure. The preferred nitrogen material is nitrogen gas and the preferred oxygen material is oxygen gas. The gas mixture is preferably energized to form a plasma which is used to contact and remove the copper oxide and clean the structure. A two-step process may be used employing a nitrogen/oxygen mixture and then a hydrogen containing gas mixture such as Ar/H2.

Abstract: The present invention provides a wafer structure having a plurality of bonding pad, an adhesion layer, a barrier layer, a wetting layer, a plurality of bump, a first passivation layer and a second passivation layer. The bonding pads are disposed on the active surface of the wafer and exposed by the first passivation layer. The second passivation layer is disposed on the first passivation layer and exposing the bonding pads. An adhesion layer is disposed on the bonding pad and covers a portion of the first passivation layer. The second passivation layer covers the first passivation layer and a portion of the adhesion layer. The barrier layer and the wetting layer are sequentially disposed on the adhesion layer and the bumps are disposed on the wetting layer.

Abstract: A method and device for avoiding oxide gouging in shallow trench isolation (STI) regions of a semiconductor device. A trench may be etched in an STI region and filled with insulating material. An anti-reflective coating (ARC) layer may be deposited over the STI region and extend beyond the boundaries of the STI region. A portion of the ARC layer may be etched leaving a remaining portion of the ARC layer over the STI region and extending beyond the boundaries of the STI region. A protective cap may be deposited to cover the remaining portion of the ARC layer as well as the insulating material. The protective cap may be etched back to expose the ARC layer. However, the protective cap still covers and protects the insulating material. By providing a protective cap that covers the insulating material, gouging of the insulating material in STI regions may be avoided.

Abstract: A multiple-channel semiconductor device has fully or partially depleted quantum wells and is especially useful in ultra large scale integration devices, such as CMOSFETs. Multiple channel regions are provided on a substrate with a gate electrode formed on the uppermost channel region, separated by a gate oxide, for example. The vertical stacking of multiple channels and the gate electrode permit increased drive current in a semiconductor device without increasing the silicon area occupied by the device.

Abstract: A complementary metal oxide semiconductor field effect transistor (CMOS-FET) image sensor. An active photosensing pixel is formed on a substrate. At least one side of the pixel has a width equal to or less than approximately 3 ?m. At least one dielectric layer is disposed on the substrate covering the pixel. A color filter is disposed on the least one dielectric layer. A microlens array is disposed on the color filter of the pixel, and the sum of the thickness of all dielectric layers and the color filter divided by the pixel width is equal to or less than approximately 1.87.

Abstract: To change a plurality of trenches to one flat empty space by two-dimensionally forming the trenches on the surface of a semiconductor substrate and then applying heat treatment to the semiconductor substrate.

Abstract: A hole is formed in an insulating film containing silicon and carbon. The insulating film has a density or a carbon concentration varying gradually in the direction of the thickness thereof.

Abstract: In a photosensitive part 10, arranged from pixels A aligned in n rows and m columns, supply wiring lines 13a and 13b, which are electrically connected and apply transfer voltages to transfer electrodes 12a to 12d, formed of polycrystalline silicon, are installed so as to cover parts of the top surfaces of light-shielded pixels D. Dead zones for installing supply wiring lines, which existed priorly at the respective end parts in a horizontal direction of a photosensitive part, can thereby be eliminated and the photosensitive part can be made wide. Also, in the case where a plurality of the solid-state image pickup devices are used upon being made adjacent each other in the horizontal direction, parts at which image pickup is not carried out can be lessened. Also, the amount of lowering of the amounts of incident light on light-shielded pixels D can be corrected based on the output signals from light-shielded pixels D or other pixels A.

Abstract: In addition to ordinary MOS gate, drain and source, a semiconductor element includes a control gate having geometry, which is defined only by a group of straight lines along a rectangular form of the MOS gate, is not defined by an oblique line and provides a nonuniform gate length at least in one of regions aligned in a direction of a gate width. A channel region formed by the control gate provides a region of strong electric fields and a region of weak electric fields. Consequently, a conductance of a whole channel region formed by the MOS gate and the control gate, i.e., a gain coefficient ? of the semiconductor element can be modulated in accordance with voltages applied to the MOS gate and the control gate.

Abstract: The invention includes a method of forming a capacitor structure. A first electrical node is formed, and a layer of metallic aluminum is formed over the first electrical node. Subsequently, an entirety of the metallic aluminum within the layer is transformed into one or more of AlN, AlON, and AlO, with the transformed layer being a dielectric material over the first electrical node. A second electrical node is then formed over the dielectric material. The first electrical node, second electrical node and dielectric material together define at least a portion of the capacitor structure. The invention also pertains to a capacitor structure which includes a first electrical node, a second electrical node, and a dielectric material between the first and second electrical nodes. The dielectric material consists essentially of aluminum, oxygen and nitrogen.

Abstract: A semiconductor device comprises a first insulating film provided over a substrate and heat-treated, a second insulating film provided over the first insulating film, and a semiconductor film provided over the second insulating film, the second insulating film and the semiconductor film being formed successively without exposing them to the atmosphere.

Abstract: The present invention provides a transistor 100 having a germanium implant region 170 located therein, a method of manufacture therefor, and an integrated circuit including the aforementioned transistor. The transistor 100, in one embodiment, includes a polysilicon gate electrode 140 located over a semiconductor substrate 110, wherein a sidewall of the polysilicon gate electrode 140 has a germanium implanted region 170 located therein. The transistor 100 further includes source/drain regions 160 located within the semiconductor substrate 110 proximate the polysilicon gate electrode 140.

Abstract: A semiconductor chip, particularly a radiation-emitting semiconductor chip, comprises an active thin-film layer in which a photon-emitting zone is formed, and a carrier substrate for the thin-film layer is arranged at a side of the thin-film layer faces away from the emission direction and is connected to it. At least one cavity via which a plurality of mesas is fashioned at the boundary between carrier substrate and thin-film layer is fashioned in the active thin-film layer proceeding from the carrier substrate.

Abstract: A hole injecting electrode composed of ITO is formed on a glass substrate. On the hole injecting electrode, a hole injecting layer composed of CuPc (copper phthalocyanine), a plasma thin film of CFx formed by plasma CVD, a hole transporting layer of NPB, and a light emitting layer are formed in the order. On the light emitting layer, an electron transporting layer is formed, and an electron injecting electrode is formed thereon.

Abstract: A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.

Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region.

Abstract: A method for producing a high quality useful layer of semiconductor material on a substrate. The method includes implanting at least two different atomic species into a face of a donor substrate to a controlled mean implantation depth to form a weakened zone therein and to define a useful layer. The implanting step is conducted to minimize low-frequency roughness at the weakened zone. Next, the method includes bonding a support substrate to the face of the donor substrate, and detaching the useful layer from the donor substrate along the weakened zone. A structure is thus formed that includes the useful layer on the support substrate with the useful layer presenting a surface for further processing. The technique also includes thermally treating the structure to minimize high-frequency roughness of the surface of the useful layer. The result is a surface having sufficient smoothness so that chemical mechanical polishing (CMP) is not needed.