Abstract: According to one embodiment, a semiconductor memory device comprises a memory cell array and a control circuit. The control circuit applies a certain potential difference to a selected one of the memory cells. The control circuit comprises a current mirror circuit, a reference current generating circuit, and a detecting circuit. The current mirror circuit produces a mirror current having a current value identical to that of a cell current flowing in the selected one of the memory cells. The reference current generating circuit produces a reference current, the reference current having a current value that differs from the current value of the mirror current by a certain current value. The detecting circuit detects transition of a resistance state of the selected one of the memory cells based on a magnitude relation of the mirror current and the reference current.

Abstract: A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals.

Abstract: According to one embodiment, a word line driving circuit includes a driver and a booster circuit. The driver drives a word line based on an output of an inverter. The booster circuit connects a boosting capacitor to a source side of a P-channel field effect transistor of the inverter to boost the potential of the word line.

Abstract: A NAND flash memory having a memory cell array formed of a plurality of blocks including memory cell transistors arranged in a matrix form. The NAND flash memory has a first bit line; a first sense amplifier connected to the first bit line, the first sense amplifier sensing or controlling a potential on the first bit line; a second bit line; and a second sense amplifier connected to the second bit line to sense or control a potential on the second bit line. The NAND flash memory has a first drain side selection gate line; a second drain side selection gate line; a third drain side selection gate line; a fourth drain side selection gate line; a first source side selection gate line; and a second source side selection gate line. The NAND flash memory has a first block; a second block; and a decoder which turns on one of the first and third drain side selection MOS transistors and turns off the other, and which turns on one of the third and fourth drain side selection MOS transistors and turns off the other.

Abstract: A content transmitting apparatus, includes: an acquisition device configured to acquire content data distributed in streaming mode; a temporary storage device configured to store temporarily the content data acquired by the acquisition device; a data control device configured to read the content data from the temporary storage device on a first-in first-out basis; an encryption device configured to encrypt in units of a predetermined amount the content data read out by the data control device; and a transmission device configured to transmit the content data encrypted by the encryption device to a predetermined receiving apparatus via a network. If the remaining capacity of the temporary storage device becomes smaller than a predetermined threshold value depending on status of the network, then the data control device discards the content data read from the temporary storage device.

Abstract: A semiconductor memory device includes a memory cell array, a controller, and a data input/output (I/O) unit. The memory cell array includes a plurality of memory cells and is configured to store data. The controller is configured to enable a write clock signal in response to an active command when a write latency of the semiconductor device is less than a reference write latency and disable the write clock signal during a disabling period in which read data is output from the semiconductor device. The data I/O unit is configured to receive data in response to the write clock signal and output the data to the memory cell array.

Abstract: A circuit for shifting an address includes a shift cell block configured to sequentially shift address signals in response to shift control signals and a control cell block configured to generate the shift control signals for activating the shift cell block in a column unit using sequentially shifted read commands or write commands.

Abstract: In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.

Abstract: In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is

Abstract: According to one embodiment, a semiconductor memory device includes a semiconductor substrate which includes a well. A memory cell array includes memory cells each including a floating gate electrode above the well and a control gate electrode above the floating gate electrode, and is configured to write data in units of pages each including memory cells connected in series and to erase data in units of blocks each includes a plurality of the pages. A control gate line is selectively electrically connected to the control gate electrodes of at least one of the blocks. A first switching element includes a current path having ends connected to the control gate line and a ground end. The well is charged, and the first switching element is turned off before the end of the discharge of the well.

Abstract: Disclosed herein is a semiconductor memory device including: a bit line and a sense line; a data storage element having a data storage state changing in accordance with a voltage applied to the bit line; a first switch for controlling connection of the sense line to the bit line; a data latch circuit having a second data holding node and a first data holding node connected to the sense line; and a second switch for controlling connection of the second data holding node of the data latch circuit to the bit line.

Abstract: According to one embodiment, a non-volatile semiconductor storage device includes a control circuit. When performing a read operation, the control circuit is configured to: apply a first voltage to a selected word line that is connected to a selected memory cell, the first voltage being a voltage between a plurality of threshold voltage distributions; apply a second voltage to a first unselected word line adjacent to the selected word line, the second voltage being not more than the first voltage; apply a third voltage to a second unselected word line adjacent to the first unselected word line, the third voltage being not less than a read pass voltage at which non-volatile memory cells become conductive; and apply the read pass voltage to a third unselected word line, the third unselected word line being an unselected word line other than the first unselected word line and the second unselected word line.

Abstract: Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.

Abstract: A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.

Abstract: The present disclosure includes devices and methods for operating resistance variable memory cells. One or more embodiments include applying a programming signal to a resistance variable material of a memory cell, and decreasing a magnitude of a trailing portion of the applied programming signal successively according to a number of particular decrements. The magnitude and the duration of the number of particular decrements correspond to particular programmed values.

Abstract: A nonvolatile memory device is operated by, inter alia, performing a program operation on memory cells belonging to a page selected from among a plurality of pages, performing a verification operation on the programmed memory cells, loading a start loop value of a fail bit count set to the selected page, from among start loop values of fail bit counts set to the respective pages, and if a loop value of the program operation is greater than or equal to the start loop value, counting a number of fail bits included in data of the programmed memory cells detected in the verification operation.

Abstract: A resistance change memory device includes memory cells including two transistors connected in parallel between a first node and a connecting node and a variable resistance element whose one end is connected to the connecting node. The first node of each memory cell and a second node, which is the other end of the variable resistance element of the memory cell, are connected to different bit lines. The first node of a one memory cell and the first node of another memory cell which is adjacent on a first side along the second axis to the one memory are connected to the same bit line. The second node of the one memory cell and the second node of still another memory cell which is adjacent on a second side along the second axis to the one memory cell are connected to the same bit line.

Abstract: Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

Abstract: A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.

Abstract: A semiconductor memory device comprises: a phase change element (RP) and a memory cell transistor (MN0) that controls writing and reading of data with respect to the phase change element (RP); the memory cell transistor (MN0) supplies a current to the phase change element (RP) based on a first potential (VPS) in a first (read) operation mode, and in a second (write) operation mode supplies a current based on the first potential (VPS), and subsequently supplies a current based on a second potential (VPP) higher than the first potential (VPS). In a write operation, consumed current is reduced.