Abstract: Apparatuses, systems, and methods for memory initiated calibration. The memory includes a termination circuit with a tunable resistor and a calibration detection circuit with a replica tunable resistor. The calibration detection circuit measures a resistance of the replica tunable resistor and provides a calibration request signal if the resistance is outside a tolerance. Responsive to the calibration request signal, a controller of the memory schedules the memory for a calibration operation.

Abstract: A method for facilitating space experiences for at least a first space user and for at least first and second different spaces, the method comprising the steps of storing first and second space experience specifications for the first and second different spaces, respectively, wherein the first and second space experience specifications indicate space affordance settings for the first and second spaces, respectively, sensing a trigger event associated with at least one of the first and second different spaces, where the sensed trigger event is associated with the first space, using the first space experience specification to control the first space affordances and where the sensed trigger event is associated with the second space, using the second space experience specification to control the second space affordances.

Abstract: A light emitting sealed body includes a housing which stores a discharge gas in an internal space and is provided with a first window portion to which first light is incident and a second window portion from which second light is emitted. The housing includes at least one flow path which is partitioned from the internal space and extends toward at least one of the first window portion and the second window portion.

Abstract: A multi-rank circuit system includes multiple transmitters each switchably coupled to a first end of a shared input/output (IO) channel and a unified receiver coupled to a second end of the shared IO channel. The unified receiver is coupled to apply a preconfigured analog reference voltage to set a differential output of the unified receiver, and further configured to apply a variable digital code to adjust the differential output according to a particular one of the transmitters that is switched to the shared IO channel.

Abstract: Disclosed herein are techniques for providing an illumination system that emits illumination into an environment while also enabling that system to be undetectable to certain types of external light detection systems. The system includes a single photon avalanche diode (SPAD) low light (LL) detection device and a light emitting device. The light emitting device provides illumination having a wavelength of at least 950 nanometers (nm). An intensity of the illumination is set to a level that causes the illumination to be undetectable from a determined distance away based on the roll off rate of the light. While the light emitting device is providing the illumination, the SPAD LL detection device generates an image of an environment in which the illumination is being provided.

Abstract: According to some embodiments, an electrostatic particle accelerator may include an assembly having a motor and support plate; an acceleration tube; one or more stage assemblies each having an alternator coupled to a common drive shaft, a power supply coupled to one of the plurality of electrodes, and an opening to receive a portion of the acceleration tube; a pressure vessel configured to enclose the acceleration tube when the pressure vessel is fastened to the support plate; and a circulator configured to pump high pressure gas into the pressure vessel. The acceleration tube can include an ion source, an extraction assembly, and a plurality of tube segments each having a plurality of electrodes and one or more power connectors attached to one of the electrodes.

Abstract: A lighting system including monitoring of input power and output power parameters to a set of lighting loads to detect power faults and/or anomalies. The set of sensing circuits include primary side and secondary side sensing circuits that communicate with a set of monitoring circuits to process the information supplied by the sensing circuits. If a fault and/or anomaly is sensed or detected, a signal is transmitted to provide an alert.

Abstract: Disclosed is a wearable device including an outer housing including a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a side surface surrounding a space between the first surface and the second surface, wherein a metal frame is formed on at least a portion of the side surface, a display having at least a portion that is exposed through the first surface of the outer housing, a printed circuit board (PCB), a communication circuit, and a ground area, wherein the metal frame is electrically connected to the communication circuit at a first point and a second point of the metal frame, and to the ground area at a third point having a different electrical length with respect to the first point and the second point, and wherein the communication circuit is configured to transmit and/or receive a signal in a first frequency band by a first electrical path formed between the first point and the third point, and a signal in a second frequency band

Abstract: There is provided a field-programmable gate array, FPGA, device (100) comprising a configurable logic block, CLB, (110) comprising a logic inverter (120) comprising a high-electron-mobility transistor, HEMT, (130), wherein the HEMT comprises: a Si substrate (384); an AlyGay-1N layer structure (380), wherein 0<y?1; a GaN layer structure (382); and a crystal transition layer structure (386) arranged on the Si substrate. The crystal transition layer comprises: a plurality of vertical nanowire structures (388) perpendicularly arranged on the Si substrate, and an AlxGax-1N layer structure (389), wherein 0?x<1, wherein the AlxGax-1N layer structure is arranged to vertically and laterally enclose the vertical nanowire structures. There is also provided an AI processing system comprising said FPGA device (100).

Abstract: A communication device for vehicle includes a housing installed in a vehicle, a communication unit housed in the housing, and a heat dissipation component provided in a heat conductive state with the communication unit. The heat dissipation component has a heat dissipation portion configured to function as an antenna of the communication unit.

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

Abstract: Methods and apparatus for implementing a control apparatus for a light fixture for externally controlling the current to the LED light emitter of a landscape LED light fixture. In an exemplary embodiment a control apparatus for controlling current to an LED light source in a landscape lighting device includes an LED driver, a user control with a control setting indicator, and a driver housing including setting indicators.

Abstract: A fault tolerant quantum computer is implementing using hybrid acoustic-electric qubits. A control circuit includes an asymmetrically threaded superconducting quantum interference devices (ATS) that excites phonons in a mechanical resonator by driving a storage mode of the mechanical resonator and dissipates phonons from the mechanical resonator via an open transmission line coupled to the control circuit, wherein the open transmission line is configured to absorb photons from a dump mode of the control circuit. Filters are included in the control circuit to suppress cross-talk errors. Additionally, frequencies and pump mode detunings for respective multiplexed control circuits are strategically selected to reduce cross-talk errors.

Abstract: A smart lamp system and method for monitoring a status of LEDs. The system can provide LED status monitoring using a logic controller communicating with at least one strip of LEDs. The system can utilize the logic controller to assign a unique identifier (ID) to the at least one strip of LEDs based on a physical position of a plurality of dual-inline package (DIP) switches incorporated within a smart lamp housing. The system can provide a hardware architecture to interface the logic controller with a power-line communication (PLC) transceiver. The system can establish a communication protocol between the PLC transceiver and a PLC receiver to efficiently communicate the statuses of the LEDs. The logic controller can generate a payload including a binary representation of the unique ID of the smart lamp and the statuses of the LEDs and transmit the payload to the PLC transceiver.

Abstract: Embodiments include a memory device with an improved calibration circuit. Memory device input/output pins include delay lines for adjusting the delay in each memory input/output signal path. The delay adjustment circuitry includes digital delay lines for adjusting this delay. Further, each digital delay line is calibrated via a digital delay line locked loop which enables adjustment of the delay through the digital delay line in fractions of a unit interval across variations due to differences in manufacturing process, operating voltage, and operating temperature. The disclosed techniques calibrate the digital delay lines by measuring both the high phase and the low phase of the clock signal. As a result, the disclosed techniques compensate for duty cycle distortion by combining the calibration results from both phases of the clock signal. The disclosed techniques thereby result in lower calibration error relative to approaches that measure only one phase of the clock signal.

Abstract: A lamp including a light source including at least one string of light emitting diodes (LEDs) within a tube body; end caps having contacts on each end of the tube body; driver electronics within the tube body including a filament detector portion provided by a passive resistance capacitor (RC) circuit that simulates the filament load of a fluorescent lamp when installed into a ballast containing fixture; and a power level selector switch in communication with the driver electronics for selecting the power level for powering the light source.

Abstract: Apparatuses including an impedance code selector are disclosed. An example apparatus according to the disclosure includes an impedance calibration circuit, an impedance code selector and a driver circuit in a data input/output circuit. The impedance calibration circuit provides a first impedance code. The impedance code selector provides either the first impedance code or a second impedance code. The driver circuit receives either the first impedance code or the second impedance code from the impedance code selector.

Abstract: A light-emitting diode (LED) luminaire phase-dimming driver comprises a first power supply circuit, a second power supply circuit, and an interface control circuit. The second power supply circuit is configured to convert a constant voltage generated from the first power supply circuit into an output direct-current (DC) voltage to dim an external LED luminaire in response to a phase-dimming signal abstracted from a phase-cut mains voltage no matter whether the external LED luminaire is originally dimmable or not. The second power supply circuit is further configured to receive a pulse-width modulation (PWM) signal and to control the output DC voltage in response to the PWM signal. The interface control circuit comprises a relay switch configured to sense the phase-dimming signal and to control switching between an intermediate voltage and the output DC voltage to operate the external LED luminaire without flickering.

Abstract: Apparatuses and methods for calibrating adjustable impedances of a semiconductor device are disclosed in the present application. An example apparatus includes a register configured to store impedance calibration information and further includes programmable termination resistances having a programmable impedance. The example apparatus further includes an impedance calibration circuit configured to perform a calibration operation to determine calibration parameters for setting the programmable impedance of the programmable termination resistances. The impedance calibration circuit is further configured to program the impedance calibration information in the register related to the calibration operation.

Abstract: An apparatus and method for ZQ calibration, including determining a strong driver circuit and a weak driver circuit, which are related to an input/output (I/O) circuit connected to a signal pin, at power-up of the I/O circuit; providing a ZQ calibration code related to a sweep code to one from among the strong driver circuit and the weak driver circuit according to ZQ calibration conditions; and providing a ZQ calibration code related to a fixed code to an unselected circuit, thereby adjusting a termination resistance of the signal pin.