Patents Examined by Anthan Tran
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Patent number: 10777253Abstract: A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.Type: GrantFiled: April 16, 2019Date of Patent: September 15, 2020Assignee: International Business Machines CorporationInventors: Riduan Khaddam-Aljameh, Manuel Le Gallo-Bourdeau, Abu Sebastian, Evangelos Stavros Eleftheriou, Pier Andrea Francese
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Patent number: 10777234Abstract: An off-chip driver including a first driving circuit is provided. The first driving circuit is used to adjust a slew rate of the off-chip driver. The first driving circuit includes a first pre-driver, a switch string, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch string is configured to perform a voltage division operation in cooperation with the first pre-driver on a power supply voltage according to the read signal, so as to generate a first output stage control signal. The first output stage generates a data signal according to the first output stage control signal.Type: GrantFiled: August 29, 2018Date of Patent: September 15, 2020Assignee: Winbond Electronics Corp.Inventor: Taihei Shido
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Patent number: 10770148Abstract: An operation method of a nonvolatile memory device includes applying a program voltage to a selected word line and programming a selected memory cell connected to the selected word line; reading an adjacent memory cell connected to an adjacent word line of the selected word line; and verifying the selected memory cell by adjusting charge sharing between the selected memory cell and a sensing node, which is connected to the selected memory cell through a bit line.Type: GrantFiled: April 23, 2018Date of Patent: September 8, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Taeck Jung, So-Yeong Gwak, Sang-Wan Nam
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Patent number: 10770125Abstract: Methods for sensing ferroelectric memory devices and apparatuses using the same have been disclosed. One such apparatus includes a ferroelectric memory cell coupled to a data line, a reference capacitance, and a common node coupled between the data line and the reference capacitance. A current mirror circuit is coupled to the data line and the reference capacitance. During a sense operation, the common node is configured to be at a fixed voltage and the current mirror circuit is configured to mirror displacement current from the reference capacitance to the ferroelectric memory cell.Type: GrantFiled: January 25, 2017Date of Patent: September 8, 2020Assignee: Micron Technology, Inc.Inventor: Adam D. Johnson
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Patent number: 10762959Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.Type: GrantFiled: May 25, 2018Date of Patent: September 1, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chung H. Lam, Scott C. Lewis, Thomas M. Maffitt, Jack Morrish
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Patent number: 10755791Abstract: According to an embodiment, a semiconductor storage device includes a first memory cell and a control circuit. The first memory cell is configured to store first data. The control circuit is configured to apply a first voltage to a source of the first memory cell in a read operation of the first data in the first memory cell, and to apply a second voltage to the source of the first memory cell in a verify operation of the first data in the first memory cell. The second voltage is lower than the first voltage.Type: GrantFiled: March 4, 2019Date of Patent: August 25, 2020Assignee: Toshiba Memory CorporationInventors: Yoshihiko Kamata, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi
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Patent number: 10748964Abstract: An electronic device and a method for fabricating the same are provided. An electronic device according to an implementation of the disclosed technology is an electronic device including a semiconductor memory, wherein the semiconductor memory includes: a plurality of first lines extending in a first direction; a plurality of second lines extending in a second direction that intersects with the first direction; a plurality of variable resistance elements disposed between the first lines and the second lines and located at intersections of the first lines and the second lines; and a plug connected to a first portion of each of the first lines, wherein the plug comprises a conductive layer and a material layer having a resistance value higher than that of the conductive layer.Type: GrantFiled: December 13, 2018Date of Patent: August 18, 2020Assignee: SK hynix Inc.Inventor: Jae-Yeon Lee
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Patent number: 10748584Abstract: Apparatuses, multi-memory systems, and methods for controlling data timing in a multi-memory system are disclosed. An example apparatus includes a plurality of memory units. In the example apparatus, a memory unit of the plurality of memory units includes a memory configured to provide associated read data to a data pipeline based on row control signals and column control signals. The memory unit further includes local control logic configured to provide the row control signals and the column control signals to the memory, and a configurable delay circuit coupled between the local control logic and the memory, the configured to delay receipt of the column control signals to the memory.Type: GrantFiled: September 19, 2018Date of Patent: August 18, 2020Assignee: Micron Technology, Inc.Inventors: Tsugio Takahashi, Zer Liang
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Patent number: 10741233Abstract: A semiconductor memory device comprises a first memory cell with a first variable resistance element. A first write controller is configured to write data into the first memory cell using a first voltage that is supplied via a first wiring. A second write controller configured to write data into the first memory cell using a second voltage that is lower than the first voltage when the first voltage supplied via the first wiring is reduced below a threshold level.Type: GrantFiled: February 27, 2018Date of Patent: August 11, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Masahiro Takahashi, Ryousuke Takizawa
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Patent number: 10734083Abstract: A voltage driver includes a voltage divider, a first transistor and a second transistor. The voltage divider is connected with a first voltage source and a second voltage source, and generates a first bias voltage. A drain terminal of the first transistor is connected with a third voltage source. A gate terminal of the first transistor is connected with the voltage divider to receive the first bias voltage. A drain terminal of the second transistor is connected with a source terminal of the first transistor. A gate terminal of the second transistor receives a second bias voltage. A source terminal of the second transistor is connected with a fourth voltage source. The first transistor and the second transistor are of the same conductivity type and match each other. The source terminal of the first transistor generates an output voltage.Type: GrantFiled: August 27, 2018Date of Patent: August 4, 2020Assignee: EMEMORY TECHNOLOGY INC.Inventors: Yu Wu, Wei-Chiang Ong, Chih-Yang Huang
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Patent number: 10720209Abstract: A resistive memory element or device includes: a first, main, memory cell area including a plurality of first resistive memory cells; and a second, buffer, memory cell area including a plurality of second resistive memory cells. The first resistive memory cells of the main memory cell area are configured to store data therein, and the second resistive memory cells of the buffer memory cell area are configured to temporarily store portions of the data therein for at least a stabilization time period while the portions of the data stabilize in the main memory cell area.Type: GrantFiled: December 5, 2018Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Hyun Kook Park, Young Hoon Oh, Chi Weon Yoon, Yong Jun Lee, Chea Ouk Lim
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Patent number: 10719122Abstract: A device in an automated environment can detect patterns in the user's interactions with accessories in the automated environment and can provide feedback to the user based on the patterns. Examples include: suggesting automation of particular actions based on the patterns; suggesting actions that conform to the pattern when the user performs part of the pattern; or suggesting changes to a pattern to conform to a preferred pattern.Type: GrantFiled: September 16, 2015Date of Patent: July 21, 2020Assignee: Apple Inc.Inventors: Lukas M. Marti, Ronald Keryuan Huang
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Patent number: 10714183Abstract: A high voltage switch circuit includes a first transistor, a first depletion mode transistor, a level shifter, a control signal generator, a second transistor and a second depletion mode transistor. The first transistor transmits the second driving voltage to an output terminal in response to a first gate signal. The first depletion mode transistor transmits the second driving voltage to the first transistor in response to feedback from the output terminal. The control signal generator generates first and second control signals in response to a level-shifted enable signal. The second transistor has a gate electrode connected to the first voltage and is turned on and off in response to the second control signal at a first end of the second transistor. The second depletion mode transistor is connected between a second end of the second transistor and the output terminal, and has a gate electrode receiving the first control signal.Type: GrantFiled: May 24, 2019Date of Patent: July 14, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong-Kyu Kim, Young-Sun Min, Dae-Seok Byeon, Ho-Kil Lee
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Patent number: 10714173Abstract: A resistive RAM (RRAM) device has a bit line, a word line, a source line carrying a bias voltage that is a substantially static and non-negative voltage, an RRAM cell, and a bit line control coupled to the bit line circuit. The RRAM cell includes a gate node coupled to the word line, a bias node coupled to the source line, and a bit line node coupled to the bit line. The bit line control circuit is configured to generate non-negative command voltages to perform respective memory operations on the RRAM cell.Type: GrantFiled: January 31, 2019Date of Patent: July 14, 2020Assignee: Hefei Reliance Memory LimitedInventor: Brent Steven Haukness
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Patent number: 10706920Abstract: A memory device includes: a memory cell array including a plurality of memory cells, wherein each of the plurality of memory cells includes a switching element, and a data storage element connected to the switching element, wherein the data storage element includes a phase change material; and a memory controller configured to perform a control operation with respect to a first memory cell of the plurality of memory cells by inputting an operating current to the first memory cell, and inputting a compensation current flowing from the data storage element to the switching element in the first memory cell before or after inputting the operating current to the first memory cell.Type: GrantFiled: August 10, 2018Date of Patent: July 7, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chea Ouk Lim, Tae Hui Na, Jung Sunwoo, Yong Jun Lee
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Patent number: 10706929Abstract: Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.Type: GrantFiled: March 23, 2018Date of Patent: July 7, 2020Assignee: SK hynix Inc.Inventors: Hee Joung Park, Kyeong Seung Kang, Won Chul Shin
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Patent number: 10693064Abstract: A semiconductor memory device according to an embodiment comprises a memory cell array configured from a plurality of row lines and column lines that intersect one another, and from a plurality of memory cells disposed at each of intersections of the row lines and column lines and each including a variable resistance element. Where a number of the row lines is assumed to be N, a number of the column lines is assumed to be M, and a ratio of a cell current flowing in the one of the memory cells when a voltage that is half of the select voltage is applied to the one of the memory cells to a cell current flowing in the one of the memory cells when the select voltage is applied to the one of the memory cells is assumed to be k, a relationship M2<2×N×k is satisfied.Type: GrantFiled: March 31, 2017Date of Patent: June 23, 2020Assignee: Toshiba Memory CorporationInventor: Kenichi Murooka
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Patent number: 10691625Abstract: A converged memory device includes: a first memory installed in an environment having a first temperature; a second memory installed in an environment having a second temperature that is lower than the first temperature; and a controller configured to selectively access the first memory or the second memory in response to a request.Type: GrantFiled: September 19, 2018Date of Patent: June 23, 2020Assignee: SK hynix, Inc.Inventors: Hyung-Sup Kim, Hyung-Sik Won
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Patent number: 10685683Abstract: A magnetic recording array includes: a plurality of domain wall moving elements; a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements; a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements; a first switching element which is connected between each of the domain wall moving elements and the first wiring; and a second switching element which is connected between each of the domain wall moving elements and the second wiring, wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element.Type: GrantFiled: March 5, 2019Date of Patent: June 16, 2020Assignee: TDK CORPORATIONInventors: Takuya Ashida, Tatsuo Shibata
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Patent number: 10678285Abstract: According to one aspect, embodiments described herein provide a system and a method for managing an electrical distribution system for a facility having at least one load. In one example, the method comprises receiving data related to transfer performance of a plurality of energy sources in the electrical distribution system, the plurality of energy sources including a first energy source and a second energy source, converting the data into transfer parameter values, receiving predefined transfer performance indicators related to the plurality of energy sources in the electrical distribution system, comparing the transfer parameter values with predefined transfer performance indicators to produce a comparison result assessing transfer performance of the plurality of energy sources, and managing transfer of the at least one load between the first energy source and the second energy source based on the comparison result.Type: GrantFiled: December 27, 2012Date of Patent: June 9, 2020Assignee: SCHNEIDER ELECTRIC USA, INC.Inventors: John C. Van Gorp, John Eggink