Abstract: In a computer system, with a system interface unit (SIU) for controlling data transfers between a lower speed main memory and either a central processor unit (CPU) or a high-speed cache memory unit (CMU), a cache memory command buffer (CMCB) circuit allows the SIU and CMU to operate independently of each other and ensures that commands to the CMU and SIU are executed in proper sequence. The CMCB circuit includes a stack sequence control scheme with circuitry for storing read and write signals from the CPU into read and write buffers and for outputting these signals to the CMU and SIU without interrupting the operation of either unit. The sequence control circuit includes an address decision network, a stack memory containing buffer pointers which indicate where the CPU read/write signals are located in the buffers, and a plurality of pointer registers or binary counters which indicate where buffer pointers (for particular read/write operations by the CMU or SIU) are located in the stack memory.