Abstract: An information recording apparatus according to the present invention manages a priority value for each host that can log in, and allocates an immediate data buffer to each host based on the priority value. The priority value changes in accordance with data transfer amount, command importance degree, etc. The information recording apparatus recalculates the priority value regularly or arbitrary, and re-performs login negotiation by requesting re-login to the hosts. The amount of buffer allocated is dynamically changed by this login negotiation, and a buffer allocation state best suited to each occasion is built. Since the present invention can dynamically determine or change the allocation amount of the immediate data buffer in accordance with the condition of each occasion, the performance of an iSCSI apparatus can be improved.

Abstract: In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of less than the predetermined number of bits for sequencing to each subsequent address. For example, the respective bit pattern for each of the addresses is cycled through in a gray code sequence. By limiting the number of transitions in the address bits, charge gain failure of a flash memory device is minimized and even may be eliminated.

Abstract: A storage control apparatus comprises a data I/O control unit which has communication ports adapted to connect with any of information processing apparatuses, is communicatively connected to physical disk drives for storing data, and performs data read/write from/to the drives according to a data I/O request received from the processing apparatus; a first memory storing a data read/written among the data stored in the disk drives; and a second memory storing information on management of storage resources including the communication ports, the physical disk drives, and a storage capacity of the first memory allocated for each user using the processing apparatuses. Upon reception of a request of the information on management from a user, an identifier of the communication port, an identifier of the disk drive, and a storage capacity of the first memory allocated for the user are transmitted to a user interface.

Abstract: A method and apparatus for testing cache coherency in a multiprocessor data processing arrangement. Selected values are written to memory by a plurality of threads, and consistency of the values in the memory with the values written by the plurality of threads is verified. Performance characteristics of the data processing system are measured while writing the values, and in response to the performance characteristics relative to target performance characteristics, parameters that control writing by the plurality of threads are selectively adjusted.

Abstract: One or more master CHN 21AM and one or more back-up CHN 21AC are provided. In each of the one or more back-up CHNs 21AC, the I/O processor 504 is in a power on state, and the NAS processor is in a power off state. The I/O processor 504 accesses a shared memory 25 periodically, and if the fact that a problem has occurred in any master CHN 21AM has been written to the shared memory 25, then the power supply of the NAS processor 506 is turned on, and processing is carried out for switching the back-up CHN 21AC in which the I/O processor 504 is installed, to a master CHN 21 AM.

Abstract: One embodiment of the present invention provides a system that avoids inconsistencies between multiple translators in an object-addressed memory hierarchy. This object-addressed memory hierarchy includes an object cache, which supports references to object cache lines based on object identifiers instead of physical addresses. During operation, the system receives a read-to-share (RTS) signal for an object cache line, wherein the RTS signal is received from a requesting processor as part of a cache-coherence operation. If no processor owns the object cache line, the system causes the requesting processor to become the owner of the object cache line instead of merely holding a copy the object cache line in the shared state.

Abstract: One embodiment disclosed relates to a method for persistently tracking volatile memory faults. A memory error is detected in relation to at least one dynamic random access memory (DRAM) unit on a particular memory module. An entry pertaining to the memory error is written in non-volatile memory of a fault storage unit on that particular memory module. Another embodiment disclosed relates to a memory module that persistently tracks volatile memory faults. The memory module includes a plurality of dynamic random access memories (DRAMs) and a fault storage unit. The fault storage unit includes non-volatile memory configured to store entries pertaining to faults in the plurality of DRAMs on that memory module.

Abstract: The present invention makes it possible to suitably create additional information on the basis of backup target data and then store the additional information in a data storage medium. In one embodiment, a system comprises a backup destination storage device (7A) that constitutes a backup destination of backup target data to be a target for backup; a backup source device (1), comprising a backup execution module (11) that backs up the backup target data by transferring the backup target data to the backup destination storage device (7A); an additional information storage medium (7P), which is capable of storing additional information created on the basis of the backup target data; and an additional information creation module (21), which creates additional information on the basis of the backup target data and stores the additional information in the additional information storage medium (7P) after a backup of the backup target data has been completed.

Abstract: One embodiment disclosed relates to a method of selecting a default locality for a memory object requested by a process running on a CPU in a multiprocessor system. A determination is made as to whether the memory object comprises a shared-memory object. If the memory object comprises said shared-memory object, then the default locality is selected to be within interleaved memory in the system. If not, a further determination may be made as to whether the memory object comprises a stack-type object. If the memory object comprises said stack-type object, then the default locality may be selected to be within local memory at a same cell as the requesting CPU. If not, a further determination may be made as to whether the requesting process has threads running on multiple cells.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, when it is determined that a cache line is being falsely shared using the performance indicators and counters, an interrupt may be generated and sent to a performance monitoring application. An interrupt handler of the performance monitoring application will recognize this interrupt as indicating false sharing of a cache line. Rather than reloading the cache line in a normal fashion, the data or instructions being accessed may be written to a separate area of cache or memory area dedicated to false cache line sharing data. The code may then be modified by inserting a pointer to this new area of cache or memory.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, the performance indicators may be utilized to obtain information regarding the nature of the cache hits and reloads of cache lines within the instruction or data cache. These embodiments may be used to determine whether processors of a multiprocessor system, such as a symmetric multiprocessor (SMP) system, are truly sharing a cache line or if there is false sharing of a cache line. This determination may then be used as a means for determining how to better store the instructions/data of the cache line to prevent false sharing of the cache line.

Abstract: A method and processor system that substantially enhances the store gathering capabilities of a store queue entry to enable gathering of a maximum number of proximate-in-time store operations before the entry is selected for dispatch. A counter is provided for each entry to track a time since a last gather to the entry. When a new gather does not occur before the counter reaches a threshold saturation point, the entry is signaled ready for dispatch. By defining an optimum threshold saturation point before the counter expires, sufficient time is provided for the entry to gather a proximate-in-time store operation. The entry may be deemed eligible for selection when certain conditions occur, including the entry becoming full, issuance of a barrier operation, and saturation of the counter. The use of the counter increases the ability of a store queue entry to complete gathering of enough store operations to update an entire cache line before that entry is dispatched to an RC machine.