Abstract: A high-k dielectric layer is formed over a semiconductor substrate having a first trench and a second trench. A barrier layer is formed over the high-k dielectric layer. A work function layer is deposited over the barrier layer, and is patterned and removed from the second trench, exposing the barrier layer at the second trench. A precursor is deposited selectively over the barrier layer in the second trench, and deposited over the work function layer in the first trench. The precursor selectively reacts with the barrier layer to selectively etch the barrier layer, and selectively reacts with the work function layer to selectively etch a top oxidized portion of the work function layer and deposit a protective layer. The reaction products between the precursor and the barrier layer, and the reaction products between the precursor and the work function layer are removed by using an inert gas.

Abstract: Methods for plasma enhanced atomic layer deposition (PEALD) of low-K films are described. A method of depositing a film comprises exposing a substrate to a silicon precursor having the general formula (I) wherein R1, R2, R3, R4, R5, and R6 are independently selected from hydrogen (H), substituted alkyl, or unsubstituted alkyl; purging the processing chamber of the silicon precursor; exposing the substrate to a carbon monoxide (CO) plasma to form one or more of a silicon oxycarbide (SiOC) or silicon oxycarbonitride (SiOCN) film on the substrate; and purging the processing chamber.

Abstract: A technique comprising: providing an assembly temporarily adhered on opposite sides to respective carriers by respective adhesive elements, the assembly including at least one plastic support sheet; heating the assembly while mechanically compressing the assembly between the carriers, wherein the strength of adhesion of one of said adhesive elements to the respective carrier and/or to the assembly is partially reduced during said heating of the assembly under mechanical compression; and wherein the strength of adhesion of the said adhesive element to the carrier and/or to the assembly is further reducible by further heating the said adhesive element after partially or completely relaxing the pressure at which the assembly is mechanically compressed between the two carriers.

Abstract: Methods of depositing material on a surface of a substrate are disclosed. The methods include exposing a surface of the substrate to a precursor within a reaction chamber to form adsorbed species on the surface and removing at least a portion of the adsorbed species prior to introducing a reactant to the reaction chamber.

Abstract: A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.

Abstract: Forming a semiconductor arrangement includes providing a first semiconductor layer having a first surface, forming a first plurality of trenches in the first surface of the first semiconductor layer, each of the trenches in the first plurality having first and second sidewalls that extend from the first surface to a bottom of the respective trench, implanting first type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, implanting second type dopant atoms into the first and second sidewalls of each of the trenches in the first plurality, and annealing the semiconductor arrangement to simultaneously activate the first type dopant atoms and the second type dopant atoms.

Abstract: There is provided a technique that includes: (a) modifying a surface of one base among a first base and a second base to be F-terminated by supplying a fluorine-containing radical generated from a fluorine-containing gas to a substrate where the first base and the second base are exposed at a surface of the substrate; and (b) forming a film on a surface of the other base, which is different from the one base, among the first base and the second base by supplying a film-forming gas to the substrate after modifying the surface of the one base.

Abstract: There is provided a technique for improving a resistance of a film to vibration in a semiconductor device having a vibrating film, including at least: forming a first silicon oxide film; forming a first silicon nitride film; forming a second silicon oxide film; and forming a second silicon nitride film, and each film formation is performed using a substrate processing apparatus configured to supply gas to a process chamber including upper and bottom electrodes, and selectively supply high frequency power or low frequency power to each of the upper and bottom electrodes by switching.

Abstract: Provided are a deposition method, a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate and a dielectric structure. The substrate includes at least one fin thereon. The dielectric structure covers the at least one fin. A thickness of the dielectric structure located on a top surface of the at least one fin is greater than a thickness of the dielectric structure located on a sidewall of the at least one fin. The dielectric structure includes a first dielectric layer and a second dielectric layer. The first dielectric layer is conformally disposed on the at least one fin. The second dielectric layer is disposed on the first dielectric layer over the top surface of the at least one fin. A thickness of the second dielectric layer is greater than a thickness of the first dielectric layer.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated circuit (IC). The method includes forming a gate electrode and a gate dielectric stacked over a substrate. A sidewall spacer layer is deposited over the substrate and the gate electrode, in which the sidewall spacer layer lines sidewalls of the gate electrode. An etching back is performed on the sidewall spacer layer to form a sidewall spacer on the sidewalls of the gate electrode. The etching back is performed at an etch rate less than about 8 angstroms/minute using an etchant comprising hydrogen fluoride. Further, the substrate is doped with the sidewall spacer and the gate electrode in place to form a pair of source/drain regions respectively on opposite sides of the gate electrode.

Abstract: A method of forming a topology-controlled layer on a patterned recess of a substrate, includes: (i) depositing a Si-free C-containing film having filling capability on the patterned recess of the substrate by pulse plasma-assisted deposition to fill the recess in a bottom-up manner or bottomless manner; and (ii) subjecting the bottom-up or bottomless film filled in the recess to plasma aching to remove a top portion of the filled film in a manner leaving primarily or substantially only a bottom portion of the filled film or primarily or substantially only a sidewall portion of the filled film.

Abstract: A method includes: receiving a first wafer; defining a first zone and a second zone on the first wafer and a plurality of first areas; defining a plurality of first areas and second areas for the first and second zones, respectively; projecting first ion beams onto the first areas and receiving first thermal waves in response to the first ion beams; rotating the first wafer by a twist angle; projecting second ion beams onto the second areas and receiving second thermal waves in response to the second ion beams; and estimating a first crystalline orientation angle of the first wafer based on the first and second ion beams and the first and second thermal waves.

Abstract: Exemplary processing methods may include forming a first deposition plasma of a silicon-and-nitrogen-containing precursor. The methods may include depositing a first portion of a silicon nitride material on a semiconductor substrate with the first deposition plasma. A first treatment plasma of a helium-and-nitrogen-containing precursor may be formed to treat the first portion of the silicon nitride material with the first treatment plasma. A second deposition plasma may deposit a second portion of a silicon nitride material, and a second treatment plasma may treat the second portion of the silicon nitride material. A flow rate ratio of helium-to-nitrogen in the first treatment plasma may be lower than a He/N2 flow rate ratio in the second treatment plasma. A first power level from a plasma power source that forms the first treatment plasma may be lower than a second power level that forms the second treatment plasma.

Abstract: The present invention relates to a vapor deposition compound capable of thin film deposition through vapor deposition, and particularly to a silicon precursor capable of being applied to ALD or CVD, and specifically, enabling high temperature deposition, and a method of manufacturing a silicon-containing thin film.

Abstract: A method of manufacturing an integrated circuit device, the method including forming a plurality of target patterns on a substrate such that an opening is defined between two adjacent target patterns; forming a pyrolysis material layer on the substrate such that the pyrolysis material layer partially fills the opening and exposes an upper surface and a portion of a sidewall of the two adjacent target patterns; and forming a material layer on the exposed upper surface and the exposed portion of the sidewall of the two adjacent target patterns, wherein, during the forming of the material layer, the material layer does not remain on a resulting surface of the pyrolysis material layer.

Abstract: A method of monitoring a dicing tape tension is described. The method includes acquiring tension data indicative of the dicing tape tension by automated optical inspection of a dicing tape.

Abstract: A method and apparatus for depositing a material on a surface of a substrate are disclosed. The method can include a treatment step to suppress a rate of material deposition on the surface of the substrate. The method can result in higher-quality deposited material. Additionally or alternatively, the method can be used to fill a recess within the surface of the substrate with reduced or no seam formation.

Abstract: Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a semiconductor substrate, a first ILD layer over the semiconductor substrate, and a first metal feature in the first ILD layer; depositing a second metal feature over the workpiece such that the second metal feature is electrically coupled to the first metal feature; patterning the second metal feature to form a first trench adjacent to the first metal feature; depositing a blocking layer over the workpiece, wherein the blocking layer selectively attaches to the first ILD layer; depositing a barrier layer over the workpiece, wherein the barrier layer selectively forms over the second metal feature relative to the first ILD layer; and depositing a second ILD layer over the workpiece.

Abstract: Semiconductor device and fabrication method are provided. A plurality of first-type fin groups and second-type fins, each between the first-type fin groups, are formed on a substrate. A first-type fin group includes first-type fins. The first-type fins and the second-type fins are arranged in a direction perpendicular to an extending direction of the first-type fins and the second-type fins. The second-type fins are removed to form first trenches between corresponding first-type fin groups. A protective layer is formed on sidewalls of the first trenches after removing the second-type fins. The protective layer covers sidewalls of the first-type fins that are perpendicular to a width direction of the first-type fins. Second trenches are formed in the substrate under the first trenches by etching the substrate at bottoms of the first trenches using the protective layer as an etch mask.

Abstract: A method includes, before attaching a window assembly to a semiconductor wafer, the semiconductor wafer including a plurality of integrated circuits and each integrated circuit including an electrical connection pad, adhering the window assembly to a carrier fixture. The method further includes, before attaching the window assembly to the semiconductor wafer, removing portions of the window assembly to create removal areas. The method then includes attaching the window assembly to the semiconductor wafer such that the electrical connection pad of each of the plurality of integrated circuits is within a removal area and removing the carrier fixture leaving the window assembly adhered to the semiconductor wafer with the electrical connection pad exposed of each of the plurality of integrated circuits.