Abstract: An asynchronous and delay-insensitive data processor comprises a plurality of components communicating with each other and synchronizing their activities by communication actions on channels and buses. Each component consists of a control part and a data part. All control parts are implemented with a lazy-active-passive handshake protocol and a sequencing means called a left/right buffer that provides the minimal sequencing constraints on the signals involved. The data parts comprise novel asynchronous ALU, buses, and registers. The control parts and data parts are connected together in an asynchronous and delay-insensitive manner.

Abstract: An operation for achieving consistency among copies existing in a plurality of cache memories in a parallel computer system was performed per transaction. If an access issued from a processor to a cache memory is a synchronous access, seeking of a DIRTY block in the cache memory is started. The cache memory issues a bus transaction onto a system bus and performs write back of the DIRTY block in the cache memory relative to a main memory. The write back bus transaction issued from the cache memory in the foregoing fashion is snooped by the other cache memory. With this arrangement, an unnecessary consistency holding operation can be omitted to reduce a delay upon memory accessing in a parallel computer system employing a loose memory consistency model.

Abstract: A method and apparatus for modeling the exposure of spacecraft-mounted solar power panels to the sun over a given time interval, such as an orbit period, and a method and apparatus for modeling the drag of spacecraft over a given time interval, such as an orbit period. The result of the exposure modeling can be used to determine varying availability of electrical power for operations to be performed by the spacecraft and on-board apparatus. The results of the drag over time are used to predict orbit decay and fuel requirements for orbit maintenance and station-keeping. The invention uses a graphically based satellite systems analysis program to approximate exposure and drag data through visual projection of the relevant spacecraft elements on a computer display screen.

Abstract: The present invention is directed to providing an ability to re-host, or port, an object oriented graphical user interface implementation from a native window-based platform, or environment, to another window-based platform, or environment. Exemplary embodiments abstract any notifications (e.g., events, state changes or "interests") which occur in the native environment as behavioral specifications. These behavioral specifications, (i.e., traits or protocols) can be used as part of a conformance negotiation to determine, during the execution lifetime of the graphical user interface, whether a particular client side object will conform with the behavioral specifications which have been abstracted from server side events associated with a different object. Where the conformance negotiation proves successful, abstract notifications can flow between particular instances of objects to model the state of the system, rather than using native implementations of events.

Abstract: Disclosed is a post exposure bake simulation method in lithography process to be used for a semiconductor fabrication unit, which has the steps of: expanding an inhibitor concentration distribution to be obtained by exposure calculation according to the boundary condition in the traverse direction; expanding the inhibitor concentration distribution in the depth direction while considering the interface reaction; calculating a Fourier-transformed inhibitor concentration distribution by fast-Fourier-transforming the expanded inhibitor concentration distribution; calculating the Fourier-transform product of the Fourier-transformed inhibitor concentration distribution and the Fourier transform of gaussian distribution; and calculating an inhibitor concentration distribution after diffusion in baking process by inverse-Fourier-transforming the Fourier-transform product by fast-Fourier-transforming.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A computer performance modeling system is provided. The modeling system includes a first and a second submodel which simulate system operations of a particular system component in minute and simple detail, respectively. A performance analysis mechanism is operatively coupled to the first and the second submodel to execute a simulation of the particular system component using the first and the second submodel. The performance analysis mechanism has a switching device for switching between the first and the second submodel during the simulation at a predetermined point in the execution of the simulation. In an alternative embodiment, the second submodel derives a specific behavior from simulation statistics collected by the first submodel. Also, the performance analysis mechanism executes a simulation of a system model having several of the particular system components by using a plurality of the first and the second submodels. A method for modeling computer performance also is provided.

Abstract: A system, method and computer program product for quickly generating responses to vast numbers and types of inputs employs a command response table that includes instructions for generating simple responses and various levels of detailed logical responses. In a preferred embodiment, the command response table provides three levels of responses: a first level of response for unintelligently responding to certain inputs, a second level of response for intelligently responding to certain input using simple commands and a third level of response for providing detailed logical responses by invoking scripts. Preferably, detailed logical responses are provided via scripts that are invoked by a script invocation instruction stored in the command response table. The command response table can include thousands of responses indexed by thousands of input messages. When an input command is received, the command response table is searched for the input command.

Abstract: An instruction cache for a superscalar processor having a variable byte-length instruction format, such as the X86 format, is organized as a 16K byte 4-way set-associative cache. An instruction store array is organized as 1024 blocks of 16 predecoded instruction bytes. The instruction bytes are prefetched and predecoded to facilitate the subsequent parallel decoding and mapping of up to four instructions into a sequence of one or more internal RISC-like operations (ROPs), and the parallel dispatch of up to 4 ROPs by an instruction decoder. Predecode bits are assigned to each instruction byte and are stored with the corresponding instruction byte in the instruction store array. The predecode bits include bits for identifying the starting, ending, and opcode bytes, and for specifying the number of ROPs that an instruction maps into.

Abstract: A design apparatus, article of manufacture, method and system are disclosed for simulating mass-produced semiconductor device behavior. Drain-to-source current values are obtained from actual semiconductor devices in response to voltage levels at the drain-to-source and gate of a semiconductor device. Semiconductor device attributes, such as channel-length doping concentration are also measured. A device simulator and process simulator are calibrated based upon the actual drain-to-source current values and measured attributes. A process simulator is run in response to simulated process parameters to obtain a plurality of simulated mass-produced semiconductor devices having varying semiconductor attributes. A device simulator is then run using the plurality of simulated mass-produced devices to obtain a plurality of I/V curves based upon the plurality of simulated semiconductor devices.

Abstract: A time-sliced hardware-based emulator including at least one of: programmable I/O assignment; programmable levels of DC voltage; programmable pull-up or pull-down resistors in the emulator on a pin-by pin basis; programmable forcing and/or disabling of value output from the emulator on each pin; programmable clocking; and programmable sample modes. An emulator is connected to a target system via a Pod System Interface (PSI), a specially designed cable, and a Pod User Interface (PUI). For data traveling from the emulator to the target system, each PSI receives up to 128 bits of data from the emulator. The cable, however, is only 32 bits wide. Therefore, the emulator multiplexes the data sent over the cable, sending eight interleaved groups of 32 bits to the PSI in accordance with a fast clock signal. Each PUI receives the groups of 32 bits from the PSI and sends them to the target system in accordance with control signals from the emulator.

Abstract: A computer performance modeling system is provided. The modeling system includes a first and a second submodel which simulate system operations of a particular system component in minute and simple detail, respectively. A performance analysis mechanism is operatively coupled to the first and the second submodel to execute a simulation of the particular system component using the first and the second submodel. The performance analysis mechanism has a switching device for switching between the first and the second submodel during the simulation at a predetermined point in the execution of the simulation. In an alternative embodiment, the second submodel derives a specific behavior from simulation statistics collected by the first submodel. Also, the performance analysis mechanism executes a simulation of a system model having several of the particular system components by using a plurality of the first and the second submodels. A method for modeling computer performance also is provided.

Abstract: A vital product data (VPD) detection circuit mountable on a substrate of a pluggable component. The circuit comprises a "parallel read" circuit for generating vital product data associated with the pluggable component, a "serial read" circuit for storing and retrieving vital product data associated with the pluggable component, and means for interconnecting the parallel and serial read circuits. The parallel read circuit preferably comprises a parallel array of transistors surface-mounted on the substrate, and the serial read circuit preferably comprises a serial EEPROM having a clock input, a set of address inputs, and a bidirectional data pin. A VPD detection mechanism may disable the parallel VPD circuitry in favor of the serial VPD detection circuitry, or vice versa, or these circuits may be enabled but activated in a mutually exclusive manner.

Abstract: A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in memory. The series includes a guest memory access instruction that indicates a guest logical address in guest address space. For each guest instruction in the series, a semantic routine of native instructions from the native instruction set is stored in memory. The semantic routines, which utilize native addresses in native address space, can be executed in order to emulate the guest instructions. In response to receipt of the guest memory access instruction for emulation, the guest logical address is translated into a guest real address, which is thereafter translated into a native physical address. A semantic routine that emulates the guest memory access instruction is then executed utilizing the native physical address.

Abstract: A method of emulating a peripheral device in a multiprocessor computer system to test device driver programs. The emulation program is loaded by a host microprocessor into one or more of the other microprocessors (target microprocessors) which are not being accessed by the operating system software. After the emulation program is loaded, control vectors to the entry point of the emulation program, where the environment in each of the target microprocessors are initialized for the emulator program. If more than one target microprocessor are utilized, then one of the target microprocessors are designated as the "master" microprocessor, which accepts interprocessor interrupts from the host microprocessor. When the device driver program running on the host microprocessor invokes an I/O command, and emulation mode is selected, then an interprocessor interrupt (IPI) is asserted to the master microprocessor.

Abstract: A method of analyzing a plurality of signal propagation delays along a plurality of signal interconnection lines within a programmable integrated circuit using a distributed electrical circuit model for the signal interconnection lines which programmably interconnect the electronic circuits forming the cooperative logic functions within the programmable integrated circuit. Load models representing such electronic circuits are incorporated into the circuit model for the signal interconnection lines, and differential nodal equations are generated in accordance with Kirchhoff's Current Law. The differential equations are converted to linear equations in which time is expressed in terms of a finite time interval, or time step.

Abstract: An improved laboratory instrument emulation network system is provided having instrument emulation stations and an instrument emulation network controller in which the emulation network system allows communication between the network controller and each instrument emulation station along a bi-directional, high-speed serial data communications network. The network system allows users at each emulation station to configure the station so as to emulate a certain instrument, i.e., voltmeter, pH meter, temperature meter, etc. The system performs real-time acquisition of raw data at each emulation station, transmits the raw data to the network controller in near-real time where it is converted into engineering units (e.g., volts, units of pH, degrees Celsius), then returns the converted data to the respective station and displays the data in either graphical or numerical format (or both), as the user selects. The converted data can also be transmitted to other emulation stations, if desired.

Abstract: In accordance with the present invention, a system for providing high-speed sequential modeling in a simulator or emulator environment is provided. The system includes a sequential control system (microprocessor board) which is attached directly to an emulator. The sequential control system cycles or operates at a higher speed than the emulator. This allows the sequential control system to execute multiple commands during each hardware emulation cycle so that the concurrent operations model within the accelerator/emulator and the sequential operations model within the sequential control system achieve a high degree of parallel operation, greatly enhancing system speed and performance. Further, the system includes direct high-speed connections between the sequential control system and the host workstation so that the control system can be programmed to execute a sequential model and/or to exchange data directly with the host without actually passing any information through the hardware emulator/accelerator.

Abstract: An operating system in a digital computer environment is run as a virtual machine on a virtual resource manager. In order to provide a more dynamic environment for the operating system, linkages are made between the operating system device drivers and the corresponding real and virtual devices of the virtual resource manager. This is accomplished by assigning a "token" to the virtual resource manager. A device dependent information file corresponding to the device is created. This file contains adapter dependent information including a hardward port address for the physical device. The "token" is placed in the operating system device driver at the time it is initiated. When the operating system device driver is "opened" to drive the device, it uses the "token" to communicate with the virtual resource manager device driver thereby accomplishing driver to driver binding.

Abstract: A method to logically serialize a plurality of independent system events in a virtual memory data processing system. Each event causes interrupt servicing routines to be executed and requires data structures that record the status of virtual pages to be updated. The system events include the interrupt that is generated as a result of a page fault, the interrupt that is generated as a result of a paging I/O completion operation that resolves a page fault, and lastly interrupts generated in response to a supervisory call to a paging service.