Abstract: An apparatus and method for allowing improved access to a memory by a processor utilizing a two strobed memory access protocol. The present invention discloses a method and apparatus for allowing a processor to request access to a memory over a communication bus, the processor retains control of the bus, and access to the memory, during the period of time it asserts an access strobe signal. The memory will respond to write or read requests to the memory during this period of time and the processor may address memory locations in a given page of the memory during this period of time. These accesses which occur during this period of time are initiated or terminated by a second access strobe signal while the first strobe remains active. This allows for more improved memory access times by holding it active during this multiple access window.

Abstract: In a data processing system including at least two processing units having different throughputs for performing sequential access upon a main storage unit, the number of elements of the main storage unit simultaneously accessed by the processing units is different, or the sequence of elements accessed by one of the processing units is reversed, thereby substantially improving the input/output throughput for the main storage unit.