Abstract: A separator of semiconductor wafers is made from polyethylene with a dissipative material and includes a first and second set of embossed cut perpendicular lines. The first set is typically parallel to the second set, and each set includes pairs of cut lines which are spaced from adjacent pairs. The depth of grid lines cut into the material allows air flow, circulation and vacuum release.

Abstract: A method for manufacturing a semiconductor device comprises etching a semiconductor substrate having an insulation film as mask using a mixed gas composed of HBr and CHF3, thereby having a reaction product composed of the semiconductor substrate and reaction gas to be adhered gradually on the side walls of the mask, and as a result creating a trench having a sufficient roundness formed to the upper end portion thereof.

Abstract: A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

Abstract: A memory cell which comprises a substrate having a top surface; a capacitor extending vertically into the substrate for storing a voltage representing a datum, said capacitor occupying a geometrically shaped horizontal area; a transistor formed above the capacitor and occupying a horizontal area substantially equal to the geometrically shaped horizontal area, and having a vertical device depth, for establishing an electrical connection with the capacitor, in response to a control signal, for reading from, and writing to, the capacitor, wherein the transistor includes a gate formed near the periphery of said horizontal device area and having a vertical depth approximately equal to the vertical device depth; an oxide layer on an inside surface of the gate; a conductive body formed inside the oxide layer, said conductive body having a top surface and a bottom surface and a vertical depth approximately equal to the vertical device depth; and diffusion regions in the body near the top and bottom surfaces and a met

Abstract: A method is disclosed for forming the lower storage node and contact for capacitors on a semiconductor wafer. The method includes an etch back process to remove a portion of the silicon oxide layer around the mouth of the contact hole to produce a rounded shoulder where the walls of the contact hole meet the face of the silicon oxide layer. When a contact plug is formed during a subsequent deposition process, the rounded shoulder results in local enlargement of the contact plug as well as filleting of reentrant corners. The contact plug therefore sustains substantially reduced mechanical stress during subsequent wafer cleaning processes. This stress reduction results in a reduced rate of lower node collapse and increased production yield of finished product.

Abstract: In the manufacture of an integrated circuit memory capacitor, an underlying hydrogen barrier layer, either electrically nonconductive or conductive, is formed on a substrate. Then, the lower electrode layer and the ferroelectric/dielectric layer are formed and selectively etched. A nonconductive hydrogen barrier layer is formed on the dielectric layer and selectively etched. After a heat treatment in oxygen, the upper electrode layer and a conductive hydrogen barrier layer are successively deposited and selectively etched. The nonconductive hydrogen barrier layer covers the capacitor except for a part of the upper electrode, and the conductive hydrogen barrier layer covers a portion where there is no nonconductive hydrogen barrier layer. Thus, the underlying barrier layer, the nonconductive barrier layer and the conductive barrier layer together completely cover the memory capacitor. The dielectric layer comprises a ferroelectric or high-dielectric constant metal oxide.