Abstract: An arrangement for enabling a sixteen bit microprocessor to transfer data to and from a peripheral unit operating in an eight bit mode includes a single OR gate for simulating an odd address so that only the low byte portion of the data bus is utilized. A subroutine in the microprocessor causes the microprocessor to act as if all addresses in the peripheral unit are even and to force the OR gate to an active state whenever the real address in the peripheral unit is odd.