Abstract: A plurality of addressable storage devices (“ASD's”) store a replicated data set. A requestor multicasts a data transfer request to the ASD's. The ASD's receive the data transfer request and cooperatively designate one of the ASD's to process the data transfer request and prevent the other ASD's from processing the data transfer request. The designated ASD satisfies the data transfer request and then communicates to the requestor an acknowledgement when the processing is completed. The ASD's maintain coherency in the replicated data set.

Abstract: A memory device includes an address pipeline configured to receive a write address at a first time and to provide the write address to a memory array at a second time, corresponding to a time when write data associated with the write address is available to be written to the array. The address pipeline may include a series of registers arranged to receive the write address and to provide the write address to the memory array. In addition, the memory device may include a comparator coupled to the address pipeline. The comparator is configured to compare the write address to another address (e.g., a read address) received at the memory device. A bypass path to the array may be provided for read addresses received at the memory device. A data pipeline is configured to receive data destined for the memory device and to provide the data to the memory array. The data pipeline may include a data bypass path which does not include the memory array.

Abstract: The present invention provides for setting the block-size suitably in each address space in order to deal with the difference of the scope within the spatial locality in the address space, and to suppress the generating of the unnecessary replacing.

Abstract: A modified MESI cache coherency protocol is implemented within a level two (L2) cache accessible to a processor having bifurcated level one (L1) data and instruction caches. The modified MESI protocol includes two substates of the shared state, which denote the same coherency information as the shared state plus additional information regarding the contents/coherency of the subject cache entry. One substate, SIC0, indicates that the cache entry is assumed to contain instructions since the contents were retrieved from system memory as a result of an instruction fetch operation. The second substate, SIC1, indicates the same information plus that a snooped flush operation hit the subject cache entry while it's coherency was in the first shared substate. Once the first substate is entered, the coherency state does not transition to the invalid state unless an operation designed to invalidate instructions is received.

Abstract: A computer and its corresponding cache system includes a cache memory, a buffer unit, and a bus transaction queue. The buffer unit includes a plurality of entries suitable for temporarily storing data, address, and attribute information of operations generated by the CPU. A first operation initiated by the load store unit buffers an operation in a first entry of the buffer unit, which initiates a first transaction to be queued in a first entry of the bus transaction queue where the first transaction in the bus transaction queue points to the first entry in the buffer unit. Preferably, the buffer unit is configured to modify the first transaction from a first transaction type to a second transaction type prior to execution in response to an event that alters the data requirements of the queued transaction. Additional utility is achieved by merging multiple store operation that miss to a common cache line into a single entry.

Abstract: A low complexity approach to DASD cache management. Large, fixed-size bands of data from the DASD, rather than variable size records or tracks, are managed, resulting in reduced memory consumption. Statistics are collected for bands of data, in order to improve upon the performance of a simple LRU replacement scheme. The statistics take the form of a single counter which is credited (increased) for each read to a band and penalized (reduced) for each write to a band. Statistics and LRU information are also collected for at least half as many nonresident bands as resident bands. In an emulation mode, control information (e.g., statistics and LRU information) regarding potentially cacheable DASD data, is collected even though there is no cache memory installed. When in this mode, the control information permits a real time emulation of performance enhancements that would be achieved were cache memory added to the computer system.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the address tag is valid and that the first data item is invalid. If, while the coherency indicator is set to the first state, the first cache detects a data transfer on the interconnect associated with the address indicated by the address tag, where the data transfer includes a second data item that is modified with respect to a corresponding data item in the system memory, the second data item is stored in the first cache in association with the address tag.

Abstract: A cache and method of maintaining cache coherency in a data processing system are described. The data processing system includes a system memory, a plurality of processors, and a plurality of caches coupled to an interconnect. According to the method, a first data item is stored in a first of the caches in association with an address tag indicating an address of the first data item. A coherency indicator in the first cache is set to a first state that indicates that the address tag is valid and that the first data item is invalid. If, while the coherency indicator is set to the first state, the first cache receives a data transfer on the interconnect associated with the address indicated by the address tag, where the data transfer includes a second data item that is modified with respect to a corresponding data item in the system memory, the second data item is stored in the first cache in association with the address tag.

Abstract: A cache memory system including a cache memory configured for coupling to a load/store unit of a CPU, a buffer unit coupled to said cache memory, and an operation queue comprising a plurality of entries, wherein each valid operation queue entry points to an entry in the buffer unit. The buffer unit includes a plurality of data buffers and each of the data buffers is associated with a corresponding address tag. The system is configured to initiate a data fetch transaction and allocate an entry in the buffer unit in response to a CPU load operation that misses in both the cache memory and the buffer unit. The cache system is further configured to allocate entries in the operation queue in response to subsequent CPU load operations that miss in the cache memory but hit in the buffer unit prior to completion of the data fetch.

Abstract: A first data item is stored in a first cache in association with an address tag indicating an address of the data item. A coherency indicator in the first cache is set to a first state that indicates that the first data item is valid. In response to another cache indicating an intent to store to the address indicated by the address tag while the coherency indicator is set to the first state, the coherency indicator is updated to a second state that indicates that the address tag is valid and that the first data item is invalid. Thereafter, in response to detection of a remotely-sourced data transfer that is associated with the address indicated by the address tag and that includes a second data item, a determination is made, in response to a mode of operation of the first cache, whether or not to update the first cache.

Abstract: A storage controller for controling access to data storage has a memory and at least one data port for a data network including host processors. The memory is programmed to define a respective specification for each host processor of a respective subset of the data storage to which access by the host processor is restricted, and each specification is associated with a host identifier stored in the memory. When the storage controller receives a data access request from a host processor, it decodes a host identifier from the data access request, and searches the memory for a host identifier matching the host identifier decoded from the request. Upon finding a match, the respective specification of the respective subset for the host processor is accessed to determine whether or not storage specified by the storage access request is contained in the respective subset. If so, then storage access can continue, and otherwise, storage access is denied.

Abstract: In a computer system, a processing unit generates a read request and sends it to a cache. If data for the read request is not in the cache, the cache forwards the request to a bus interface unit. If the forwarded request does not fall within the address range of any bus read transaction stored in the bus interface unit, the bus interface unit stores a new bus read transaction corresponding to the forwarded request and sends an identifier for the new transaction to the processing unit. In one preferred embodiment, if the forwarded request falls within the address range of one of the bus read transactions stored in the bus interface unit, the bus interface unit discards the forwarded request and sends an identifier for the one transaction to the processing unit. Additionally, a method of processing read requests is provided. A read request is stored in a buffer and sent to a cache.

Abstract: A data storage system includes redundant write caches, a disk controller and an array of disks. One of the redundant write caches is a primary write cache of RAM or NVRAM, and another is a backup write cache having a hybrid memory structure of a relatively small amount of NVRAM in combination with a cache-disk space mapped to disk. The cache-disk space may be located on a single disk within the disk array, or distributed over a number of the plurality of disks in the array. In one embodiment, the array of disks can may be configured as a RAID architecture. The data storage system of the present invention preferably employs a conventional, fast-write-fast-read primary write cache and a non-volatile, hybrid memory backup write cache. The redundant write caches are asymmetric since the primary write cache and the backup write cache have different sizes and structures.