Abstract: Apparatuses and methods for adaptive control of memory are disclosed. One example apparatus includes a memory translation unit configured to receive a memory access request including a requested address and to determine a mapping state of a region of a memory associated with the requested address. The memory translation unit further configured to provide a mapped address to the memory. The mapped address is selected from one of the requested address or a translated requested address based on the state of the region of the memory associated with the requested address.

Abstract: Methods that can facilitate more optimized relocation of data associated with a memory are presented. In addition to a memory controller component, a memory manager component can be employed to increase available processing resources to facilitate more optimal execution of higher level functions. Higher level functions can be delegated to the memory manager component to allow execution of these higher level operations with reduced or no load on the memory controller component resources. A uni-bus or multi-bus architecture can be employed to further optimize data relocation operations. A first bus can be utilized for data access operations including read, write, erase, refresh, or combinations thereof, among others, while a second bus can be designated for higher level operations including data compaction, error code correction, wear leveling, or combinations thereof, among others.

Abstract: One of the major artifacts that pushed Information Technology companies ahead of its competitors is undoubtedly contextual domain knowledge. When a new development problem comes to an IT team, how problem solving and steps of action can be automatically formulated is the major area of research. A method and system for utilizing domain knowledge to identify solution to a problem has been provided. The problem is reformulated as recommending a workflow like a pipeline of connected steps, by leveraging contextual domain knowledge and technical knowledge, finally planning and scheduling solutions steps, given a problem of a domain & use case. This is achieved by Contextual sequence-aware recommendation of steps, backed by semantic web technologies and pattern recognition steps. Finally a plan is derived by automated planning techniques which can be executed based on software orchestration by connecting a repository of re-usable annotated code blocks.

Abstract: In response to receiving a read request for target data, an external address of the target data is obtained from the read request, which is an address unmapped to a storage system; hit information of the target data in cache of the storage system is determined based on the external address; and based on the hit information, an address from the external address and an internal address for providing the target data is determined. The internal address is determined based on the external address and a mapping relationship. Therefore, it can shorten the data access path, accelerate the responding speed for the data access request, and allow the cache to prefetch the data more efficiently.

Abstract: A method is used in managing deduplication characteristics in a storage system. Deduplication entries stored in a deduplication cache are categorized into a set of deduplication groups based on a data deduplication probability associated with the deduplication entries. A machine learning system is used to dynamically adjust deduplication characteristics associated with the set of deduplication groups based on an I/O workload associated with the storage system.

Abstract: Examples herein describe an accelerator device that shares the same coherent domain as hardware elements in a host computing device. The embodiments herein describe a mix of hardware and software coherency which reduces the overhead of managing data when large chunks of data are moved from the host into the accelerator device. In one embodiment, an accelerator application executing on the host identifies a data set it wishes to transfer to the accelerator device to be processed. The accelerator application transfers ownership from a home agent in the host to the accelerator device. A slave agent can then take ownership of the data. As a result, any memory operation requests received from a requesting agent in the accelerator device can gain access to the data set in local memory via the slave agent without the slave agent obtaining permission from the home agent in the host.

Abstract: A data storage device including a first non-volatile memory configured to store data, and a device controller configured to control the first non-volatile memory may be provided, and wherein the device controller may be configured to receive a data read command including a first logical address of the first non-volatile memory, a first physical address corresponding to the first logical address, and first status information of the first non-volatile memory corresponding to the first physical address, determine a first read level, using the first status information included in the data read command, and apply a voltage of the first read level to a first word line of the first non-volatile memory corresponding to the first physical address to read data.

Abstract: Technologies for providing deduplication of data in an edge network includes a compute device having circuitry to obtain a request to write a data set. The circuitry is also to apply, to the data set, an approximation function to produce an approximated data set. Additionally, the circuitry is to determine whether the approximated data set is already present in a shared memory and write, to a translation table and in response to a determination that the approximated data set is already present in the shared memory, an association between a local memory address and a location, in the shared memory, where the approximated data set is already present. Additionally, the circuitry is to increase a reference count associated with the location in the shared memory.

Abstract: An embodiment of a memory controller device includes technology to control access to a multi-level memory including at least a first level memory and a second level memory, provide direct access to the first level memory based on a system memory address, cache accesses to the second level memory in a second portion of the first level memory, and address a memory space with a total memory capacity which includes a first capacity of the first portion of the first level memory plus a second capacity of the second level memory. Other embodiments are disclosed and claimed.

Abstract: A data storage device is disclosed comprising a non-volatile storage medium (NVSM), and control circuitry configured to receive a plurality of access commands, process the plurality of access commands using a customer prediction model to predict a customer of the data storage device, wherein the customer prediction model is trained off-line based on access patterns of a plurality of different customers. The control circuitry then configures access to the NVSM based on the predicted customer.

Abstract: An apparatus is provided for determining, for use in a tag-guarded memory, a selected tag value from a plurality of tag values. The apparatus comprises ordered list generation circuitry to receive an excluded tag vector comprising a plurality of fields, where each field is associated with a tag value and identifies whether the associated tag value is excluded from use. The ordered list generation circuitry is arranged to generate, from the excluded tag vector, an ordered list of non-excluded tag values. The apparatus further comprises count determination circuitry to determine, using the excluded tag vector and an identified start tag value, a count value indicative of a number of non-excluded tag values occurring in a region of the excluded tag vector bounded by an initial field and a field corresponding to the start tag value.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a program operation occurs, the controller is configured to determine a decode time for the data prior to programming the data to the memory device. The decode time determined by decoding the encoded data. A number of program loop cycles is determined using the decode time. The data is programmed to the memory device with the number of program loop cycles determined.

Abstract: Methods, systems, and devices for integrating a pivot table in a logical-to-physical mapping of a memory system are described. The memory system may receive a read command and read a first entry of a first subset of mapping and a second entry of a second subset of mapping. The second entry may include at least a portion of a pivot table associated with physical addresses of a non-volatile memory device. The memory system may retrieve data from a physical address identified in the pivot table, rather than access a different portion of the logical-to-physical mapping. The memory system may transmit, to a host system, the data retrieved from the physical address identified in the pivot table.

Abstract: A method, computer program product, and computing system for during a high IOPs period, receiving content to be written to a storage system; storing the content to a specific location within a storage device associated with the storage system; updating a temporary map to include an entry that defines the specific location of the content; and during a subsequent period, binding the content with respect to the storage device.

Abstract: A method, computer program product, and computing system for dividing a plurality of volumes replicated across a pair of storage systems into one or more consistency groups. A polarization state may be defined for each consistency group. An input-output (IO) failure associated with at least one consistency group may be detected. At least a portion of the at least one consistency group may be polarized based upon, at least in part, the polarization state defined for the at least one consistency group.

Abstract: Disclosed embodiments provide a technique in which a memory controller determines whether a fetch address is a miss in an L1 cache and, when a miss occurs, allocates a way of the L1 cache, determines whether the allocated way matches a scoreboard entry of pending service requests, and, when such a match is found, determine whether a request address of the matching scoreboard entry matches the fetch address. When the matching scoreboard entry also has a request address matching the fetch address, the scoreboard entry is modified to a demand request.

Abstract: Methods, non-transitory machine readable media, and computing devices that use extended physical region page (PRP) lists to improve storage device performance are disclosed. With this technology, a PRP list is generated that includes pointers retrieved from a scatter/gather list (SGL) for memory buffers representing data segments associated with a storage operation. The PRP list is extended to include a pointer to an allocated memory page configured to store metadata segments represented by other memory buffers referenced by other pointers in the SGL. A command request that includes the extended PRP list is submitted to a storage device for execution of the storage operation. With this technology, storage operations are advantageously enabled for non-volatile memory express (NVMe) solid-state drive (SSDs), for example, that do not support SGL transfers.

Abstract: A balloon memory fragmentation reduction system includes a memory, at least one processor in communication with the memory, a guest operating system (OS) including a device driver, and a hypervisor executing on the at least one processor. The hypervisor is configured to record an amount of memory allocated by the device driver of the guest OS, locate a contiguous region of guest memory addresses according to the amount of memory allocated by the device driver, reserve the contiguous region of guest memory addresses, and notify the guest OS that the contiguous region of guest memory addresses is reserved.

Abstract: There are provided a memory controller and an operating method thereof. The memory controller includes: a meta data storage for storing meta data including mapping information of data stored in a memory device and valid data information representing whether the data stored in the memory device is valid data; and a migration controller for controlling the memory device to perform a migration operation of moving, to a target memory block, valid data stored in a plurality of source memory blocks included in the memory device, based on the meta data. The migration controller controls the memory device to read a second valid data stored in the second die before reading a first valid data stored in the first die, based on a comparison result between a reference time and a delay time required until before the first valid data is read.

Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, controller, memory, wireless communication function section, and extension register. The controller controls the nonvolatile semiconductor memory device. The memory is serving as a work area of the controller. The wireless communication module has a wireless communication function. The extension register is provided in the memory. The controller processes a first command to read data from the extension register, and a second command to write data to the extension register. The extension register records, an information specifying the type of the wireless communication function in a specific page, and an address information indicating a region on the extension register to which the wireless communication function is assigned.