Abstract: A semiconductor package and method for manufacturing the same is disclosed. The semiconductor package comprises a semiconductor chip, a circuit board, an electrical connection means, an encapsulation material and a plurality of conductive balls. The semiconductor chip has a first surface and a second surface. A plurality of input and output pads are formed on one of the first and second surfaces. The circuit board comprises a thin film having a first surface and a second surface and being provided with a center hole in which the semiconductor chip is positioned, a plurality of circuit patterns being formed on the first surface of the thin film and including a plurality of bond fingers and ball lands, and a cover coat covering the circuit board except for the bond fingers and the ball lands. The electric connection means electrically connects the input and output pads of the semiconductor chip with the bond fingers of the circuit board.

Abstract: The invention includes a semiconductor device, comprising a silicon carbide substrate comprising micropipes, wherein the micropipes are filled with a dielectric, and a method of making such a device.

Abstract: A method of manufacturing a device separation film in a semiconductor device is disclosed. In a process technology in which a trench is formed in a silicon substrate, silicon is grown at the bottom of the trench by SEG method in order to lower the aspect ratio and the trench is then filled with an insulating material so that voids are not generated. In order for silicon to be normally grown, a thermal oxide film formed at the bottom of the trench must be removed without removing the oxide film from the sides of the trench. The disclosed method reduces the speed of forming a thermal oxide film at the bottom of the trench, by plasma process using CF4 and O2 gas after forming the trench. Thereby facilitating the removal of the thermal oxide film at the bottom of the trench while minimizing loss of the thermal oxide film at the sidewall of the trench.

Abstract: In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

Abstract: A semiconductor device comprises an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device. The edge portion comprises a substrate region (12) of a first semiconductor type. The voltage termination structure comprises at least one first termination region (11) of a second semiconductor type, the or each first termination region having at least one of either second and third termination regions (11a, 11b) of third and fourth semiconductor types located at substantially opposing edges thereof. The second and third termination regions (11a, 11b) respectively have a higher semiconductor doping concentration than the edge portion substrate region (12) and a lower semiconductor doping concentration than the first termination region(s) (11).

Abstract: A microstructure and method for forming the microstructure are disclosed. The method includes: providing a handle substrate; providing a device substrate in which high-aspect-ratio structures and optional integrated circuitry will be fabricated; forming one or more filled isolation trenches within a recessed cavity on a first surface of the device substrate or alternatively forming one or more filled isolation trenches on a first surface of the device substrate and forming a recessed cavity on a first surface of the handle substrate; bonding the first surface of the device substrate to the first surface of the handle substrate; removing a substantially uniform amount of material from the second surface of the device substrate to expose at least one isolation trench; optionally forming circuits and interconnection on a second surface of the device substrate; and etching a set of features in the second surface of the device substrate to complete the definition of electrically isolated structural elements.

Abstract: A method of manufacturing a solder bump on a power copper structure and resultant device is disclosed. In the method, a layer of an electrically conductive, non-wettable material such as TiW is applied over a power copper structure. Then, solder bumps are formed on the non-wettable layer. The presence of the non-wettable layer prevents the collapse of the solder bumps when heated.

Abstract: Bolometric detector with intermediate electrical insulation and manufacturing process for this detector. According to the invention, at least two electrodes are formed facing the same face of a layer of bolometric material (5) and starting from the same layer of conducting material (8). Areas (8A, 8B) belonging to the two electrodes are electrically isolated from each other and electrically isolated from the layer of bolometric material, while other areas (7A, 7B) belonging to the two electrodes are separated from each other and are in electrical contact with this layer. The invention is particularly applicable to infrared imagery.

Abstract: A semiconductor device comprises an active area with a voltage termination structure located adjacent to the active area at an edge portion of the device. The edge portion comprises a substrate region (23, 24) of a first semiconductor type, and the voltage termination structure comprises first and second layers (21 and 22) formed within the substrate region. The first and second layers (21 and 22) define regions each of a second semiconductor type.

Abstract: A composite dielectric layer and method of forming the composite dielectric layer for the passivation of exposed copper in a copper damascene structure are described. The composite layer consists of a passivation dielectric layer and an etch stop dielectric layer and is formed over the exposed copper prior to the deposit of an inter-metal or final passivating dielectric layer. Via holes are etched in the inter-metal or final passivating layer and the composite dielectric layer provides an etch stop function as well as passivation for the exposed copper conductor. A thin layer of passivation dielectric, such as silicon nitride, is formed directly over the exposed copper to passivate the copper. A thin layer of etch stop dielectric, such as silicon oxynitride, is then formed over the layer of passivation dielectric. The passivation dielectric is chosen for passivation properties and adhesion between the passivation dielectric and copper. The etch stop layer is chosen for etch stop properties.

Abstract: A semiconductor device comprises a semiconductor element having a signal electrode and a ground electrode. A mounting part metallic film has a bottom area on which the semiconductor element is mounted and a stepped area located at a periphery of the bottom area and being higher in horizontal level than the bottom area. A connector part metallic film is spaced from the mounting part metallic film and arranged at a peripheral region thereof. The signal electrode of the semiconductor element is electrically connected to the connector part metallic film and the ground electrode of the semiconductor element is electrically connected to the stepped area of the mounting part metallic film. The semiconductor element is shielded with resin together with mounting/connecting sides of the mounting part metallic film and the connector part metallic film.

Abstract: A multispectral detector is grown epitaxially on a substrate such as InP, GaAs, or Si and comprises sets of multi-quantum well layers. In the method of the subject invention, contact layers are grown on the substrate and on top of the active layers. The active layers comprise one or more sets of multiquantum well layers grown adjacent to each other. The active layers and multiquantum wells and consist of well and barrier layers prepared from various stochiometric ratios of InGaAlAs and InGaAsP, with the barrier layers of InAlAs and InP, or well layers GaInP interspersed with barrier layers of GaxIl−xAsyPl−y(0≦x≦1, 0≦y≦1).

Abstract: A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1×10−7 to about 1×10−5 Torr at a temperature of from about 850° C. to about 1000° C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers.

Abstract: A semiconductor device having a structure in which the potential of a gate interconnection is not affected by that of a bit line when a dummy pad contact is formed at an end portion of a memory cell, and a method of manufacturing a semiconductor device in which no steps are formed in the vicinity of a memory cell end are obtained. The semiconductor device includes dummy pad contacts arranged in a dotted line, which are smaller than a first pad contact in the memory cell body and are opened using a self-alignment method, and a conduction is cut-off in a path leading from the dummy pad contact to the bit line.

Abstract: The invention includes methods of restricting diffusion between materials. First and second different materials which are separated by a barrier layer capable of restricting diffusion of material between the first and second materials are provided. The barrier layer is formed by forming a first layer of a third material over the first material. A second layer of the third material is formed on the first layer. The second material is formed over the second layer of the third material. In another aspect, the invention relates to diffusion barrier layers. In one implementation, such a layer comprises a composite of two immediately juxtaposed and contacting, yet discrete, layers of the same material. In another aspect, the invention relates to integrated circuitry. In one implementation, a semiconductive substrate has a conductive diffusion region formed therein.

Abstract: A method of forming a semiconductor memory device using a double layered capping pattern and a semiconductor memory device formed thereby are provided. A plurality of interconnection patterns are formed on a semiconductor substrate. Each of the interconnection patterns includes a interconnection line and a double layered capping pattern. The double layered capping pattern includes a first capping pattern and a second capping pattern, which are sequentially stacked. The second capping pattern is formed of a material layer having an etching selectivity with respect to the first capping pattern. A planarized separating layer is formed between the adjacent interconnection patterns. The substrate having the planarized separating layer is covered with a sacrificial layer. The sacrificial layer is formed of a material layer having a wet etching selectivity with respect to the planarized separating layer.

Abstract: A high performance unary digital loudspeaker system is disclosed; providing cost-effective and efficient performance, and providing the option to integrate multiple speaker elements or other related circuitry, and comprising a semiconductor substrate (102), an electrode (104) disposed upon the substrate, an insulator element (106) disposed upon the electrode forming a frame of material, an electrically conductive membrane (108) disposed upon the insulator element so as to form a chamber (110) between the electrode and the membrane, the membrane having a flexible support section (112) formed therein, and a control circuit (200) coupled (114, 116) to the membrane and the electrode, and adapted to provide a variable potential therebetween.

Abstract: A semiconductor device comprises an insulated circuit board which includes a terminal electrode disposed on the rear surface or at a plane between the rear surface and the front surface thereof. An opening is formed in the insulating circuit board in such a manner as to reach the terminal electrode. A semiconductor substrate including an electrode pad is mounted on the insulated circuit board in such a manner that the electrode pad faces to the terminal electrode. A non-conductive resin is interposed in a gap between the semiconductor substrate and the insulated circuit board. The electrode pad on the semiconductor substrate is electrically connected to the terminal electrode via a connecting conductor inserted in the opening.

Abstract: A semiconductor device having a heat dissipation plate which is lighter in weight and smaller in thickness than the conventional metal plate while ensuring a good thermal dissipation and mechanical support, which comprises: a semiconductor chip having a back surface bonded to a lower surface of a heat dissipation plate having an area larger than that of the semiconductor chip; a wiring board composed of a substrate having an upper surface with conductor patterns formed thereon, the conductor patterns having first ends connected to external connection terminals downwardly penetrating through the substrate via through holes extending through the substrate, the external connection terminals being disposed between a periphery of the semiconductor chip and a periphery of the wiring substrate; the semiconductor chip and the wiring board being bonded to each other so that electrode terminals formed on an active surface of the semiconductor chip are electrically connected to second ends of the conductor patterns; and

Abstract: By appropriately selecting the structure of top gate type or staggered type TFTs disposed in the respective circuits of a semiconductor device depending on the function of the circuits, the operating characteristics and the reliability of the semiconductor device is improved. An LDD region (107) the whole of which overlaps a gate electrode is provided in a first n-channel type TFT of a controlling circuit. LDD regions (111) and (112) at least part of which overlaps a gate electrode are provided in a second n-channel type TFT of the control circuit. LDD regions (117) to (120) which do not overlap a gate electrode through offset regions are provided in an n-channel type TFT of a pixel matrix circuit. By making different the concentration of LDD regions of the control circuit and the concentration of the pixel matrix circuit, optimized circuit operation is obtained.