Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator (VCO) signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and least-squares estimate a frequency based on the quantized phase values and the wraparound phase.

Abstract: In a transmitter, first and second sets of discrete multitone (DMT) sub-carrier signals or tones are identified. First and second bit groups of a payload data frame corresponding to the first and second sets of tones are selected. The first bit group is then trellis encoded. The second bit group is not trellis encoded. The first trellis coded tone group and the second bit group are then constellation mapped to produce a DMT symbol for transmission. A receiver may use an estimate of signal-to-noise ratio (SNR) of each tone to determine whether to select the tone for inclusion in the first or second set of tones. The receiver may provide the transmitter with information indicating whether a tone is included the first or second set of tones.

Abstract: In a communication system, a method and an accompanying apparatus determine a number of available fingers (110A-N) in a receiver (100). A controller (121) adjusts a threshold based on the determined number of the available fingers (110). The adjusted threshold may be one of, or any combination of, a pilot signal search threshold, a lock/unlock threshold, and a combine/un-combine threshold. The number of available fingers (110) may change after the threshold is adjusted.

Abstract: Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.

Abstract: Techniques for calibrating the transmit and receive chains at a wireless entity are described. For a pre-calibration, N first overall gains for a receiver unit and N transmitter units in the transmit chain are obtained, where N>1. Each first overall gain is for a combined response for the receiver unit and the associated transmitter unit. N second overall gains for a transmitter unit and N receiver units in the receive chain are also obtained. Each second overall gain is for a combined response for the transmitter unit and the associated receiver unit. The gain of each transmitter unit and the gain of each receiver unit are determined based on the first and second overall gains. At least one correction matrix is then derived based on the gains of the transmitter and receiver units and is used to account for the responses of these units.

Abstract: A method for providing digital adaptive predistortion in a subscriber station is provided that includes applying predistortion, based on a set of predistortion characteristics, to a transmit signal to generate a predistorted signal. An amplifier input signal is generated based on the predistorted signal. The amplifier input signal is amplified to generate an amplified signal. The amplified signal is sampled to generate a sampled signal. The sampled signal is processed through a receive channel of the subscriber station to generate a processed signal. A determination is made regarding whether to adjust the set of predistortion characteristics based on the processed signal.

Abstract: The invention relates to a method and a circuit for carrier control in a quadrature demodulator, wherein a complex-value input signal (I, Q) is supplied to a mixer (1) to perform mixing with a mixing frequency (fm) to create a mixed signal (Ir, Qr), the mixed signal (Ir, Qr) is supplied to a processing section (s) to generate a processed signal (Ie, Qe), the processed signal (Ie, Qe) is supplied to phase measurement device (3) in order to measure a phase (?m) of the processed signal (Ie, Qe) and the measured phase (?m) is supplied to a phase controller (4) in order to control the mixing frequency (fm); wherein an idle time (z?d) is created at least during the processing in the processing section (2).

Abstract: Methods and systems for filtering include accessing first and second signals produced from an input signal and producing first and second filtered outputs, which correspond to the first and second signals, based on a filtering characteristic. The filtering characteristic can include a first filtering coefficient weighting the first and second signals. The filtering characteristic can include a second filtering coefficient weighting third and fourth signals, the third and fourth signals being produced prior to the first and second signals. The first and second filtering coefficients can include matrices which have non-symmetrical terms.

Abstract: The gain control method for the RF and IF amplification stages of a bursty data frame reception system enables, following a step for evaluating the received signal strength, the gain adjustment step of the RF amplification stage to be temporarily deferred until a frame structure symbol is received, during which the gain adjustment step of the IF amplification stage takes place simultaneously with that of the RF gain, while retaining an overall gain linearly dependent on the input signal strength.

Abstract: This is a data reproduction circuit for receiving data and reproducing the data and its clock which has an over-sampling determination circuit for sampling the received data by a clock with frequency higher than the data rate of the received data and converting the sampled data into digital signals, a circuit for selecting and outputting the reproduced data, a phase error detection circuit for detecting a phase error from its timing deviation with the received data, based on the reproduced clock, a data selection circuit for adjusting its phase, based on the output of the phase error detection circuit, a phase adjustment circuit for adjusting the phase of the reproduced clock to reproduce a new clock and a clock generation circuit for supplying the over-sampling determination circuit and the data selection circuit with the newly reproduced clock.

Abstract: Method in a diversity antenna GMSK receiver of determining interference canceling equalizers and corresponding equalizers are described. The method includes providing a plurality of GMSK received signals; de-rotating and splitting each of the plurality of received signals into in phase and quadrature parts to provide a multiplicity of real valued branches; calculating linear equalizers for each of a multiplicity of subsets of the multiplicity of real valued branches; and providing an interference canceling equalizer for each of the multiplicity of real valued branches, each interference canceling equalizer corresponding to a weighted combination of the linear equalizers. A corresponding equalizer includes eight linear equalizers processing four branch signals corresponding to real (I) and quadrature (Q) parts of a GMSK diversity signal from two antennas.

Abstract: A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.

Abstract: Hardware allocation techniques are described for use in a multi-channel communication environment. The techniques may be used to reduce the number of gates needed for processing and/or to improve the efficiency and/or speed of a communication system. For example, resources that are under-utilized may be removed or allocated to another operation or user. In an exemplary implementation, a receiver includes a plurality of signal processing modules corresponding to respective channels and a hardware allocation module. The hardware allocation module allocates resources in the signal processing modules based on utilization of at least one of the resources.

Abstract: A method used in an adaptive survivor based channel equalizer, the method comprises selecting at a decision time a survivor in a Viterbi trellis and a corresponding equalizer, adaptively updating at the decision time the corresponding equalizer to define a new corresponding equalizer for use at a next decision time, retrieving the new corresponding equalizer as defined at an earlier decision time, and using the new corresponding equalizer as defined at an earlier decision time as an equalizer for other survivors in the Viterbi trellis at the next decision time. A corresponding adaptive survivor based channel equalizer includes a fixed pre-filter configured to provide a pre-filtered signal to a reduced state sequence estimator (RSSE) which is configured for providing recovered symbols. A coefficient adaptor is coupled to the RSSE and configured to essentially perform the method.

Abstract: A GMSK receiver with interference cancellation includes a linear equalizer configured to be coupled to a received signal from a first antenna and to provide first soft bits, an adaptive estimator, e.g., adaptive MLSE coupled to the first soft bits and configured to provide second soft bits; a quality assessor coupled to the first soft bits and configured to provide a quality indication; and a switching function coupled to the linear equalizer and the adaptive MLSE and controlled in accordance with the quality indication to provide output soft bits corresponding to at least one of the first soft bits and the second soft bits. The GMSK receiver can be extended to multiple antennas and corresponding methods for interference cancellation in a GMSK signal are discussed.

Abstract: Methods and systems that are capable of detecting and correcting the sampling frequency offset as part of signal synchronization in MIMO OFDM systems. An exemplary MIMO OFDM system includes a transmitter with a number of OFDM modulators that provide data to antennas for transmission across a channel to a receiver. The OFDM modulators include a training symbol inserter that may insert a matrix of pilot tones into the data. The data including the matrix of pilot tones is received by a receiver having a number of OFDM demodulators including a synchronization circuit. The synchronization circuit uses the matrix of pilot tones to detect and correct the sampling frequency offset as part of the signal synchronization. The synchronization circuit may apply an open loop process including sampling frequency offset estimation, phase rotation, and channel estimation.

Abstract: A transmitter is provided which effectively reduces a peak that occurs in transmitting signal electric power. A baseband limiter applies a peak reduction process to digital signals on a plurality of carriers in a baseband. A band limiting filter applies a band limitation process to the digital signal on each of the carriers to which the peak reduction process is applied. Quadrature modulation processing is applied to the digital signal on each of the carriers to which the band limitation process is applied. The digital signals on the carriers to which the quadrature modulation process is applied are added. An intermediate frequency limiter multiplies a signal of the added result by a window function that is weighted depending on the magnitude of the detected peak, and applies a peak reduction process thereto.

Abstract: A method of filtering to remove coding artifacts introduced at block edges in a block-based video coder, the method having the steps of: checking the content activity on every line of samples belonging to a boundary to be filtered and where content activity is based on a set of adaptively selected thresholds determined using Variable-Shift Table Indexing (VSTI); determining whether the filtering process will modify the sample values on that particular line based on said content activity; and selecting a filtering mode between at least two filtering modes to apply on a block boundary basis, implying that there would be no switching between the two primary modes on a line by line basis along a given block boundary. The two filtering modes include a default mode based on a non-recursive filter, and a strong filtering mode which features two strong filtering sub-modes and a new selection criterion that is one-sided with respect to the block boundary to determine which of the two strong filtering sub-modes to use.

Abstract: A data transceiver and method thereof are disclosed. The data transceiver generates a gated control signal according to a valid signal and a clock signal. The packets are outputted according to the gated control signal.

Abstract: A video encoding method and apparatus is shown wherein image information is represented as a plurality of pixels, the pixels are organized into blocks, pixels transposition is performed on image information at the boundaries of the blocks, the blocks are transform coded and quantized. Pixel transposition involves transposition of alternate pixels at the boundaries of blocks with pixels of neighboring blocks found in a pre-determined direction. The pre-determined direction may be fixed by a system or may be applied on an image by image basis. In the event that the pre-determined direction is not established by a system, a pixel transposition circuit includes a transposition keyword in the output bit stream which is used by a decoded to determine the direction of pixel transposition.