Abstract: In a data synchronizer a timing error estimator samples a received data stream and generates a clock to provide optimal sampling of the data stream, and a lock detector monitors the clock and received data stream to provide an indication of whether optimal sampling has been achieved. The lock detector processes differences between delayed versions of the input which are sampled based upon the clock timing. These sampled differences are then processed by a non-linear circuit to provide a lock signal indication which, when compared to a predetermined threshold signal, is used to provide optimal sampling indication. The lock detector performs computations on real and complex inputs and therefore is compatible with a wide variety of modulation types. The lock detector can be implemented in either analog or digital circuits, making it applicable to a broad range of data synchronizer applications.

Abstract: The instantaneous V.sub.co signal on a charging capacitor is sampled and the charge voltage on capacitor C.sub.o is captured just prior to its discharge into the first stage of magnetic modulator. The captured signal is applied to an averaging circuit with a long time constant and to the positive input terminal of a differential amplifier. The averaged V.sub. co signal is split between a gain stage (G=0.975) and a feedback stage that determines the slope of the voltage ramp applied to the high speed comparator. The 97.5% portion of the averaged V.sub.co signal is applied to the negative input of a differential amplifier gain stage (G=10). The differential amplifier produces an error signal by subtracting 97.5% of the averaged V.sub.co signal from the instantaneous value of sampled V.sub.co signal and multiplying the difference by ten. The resulting error signal is applied to the positive input of a high speed comparator.

Abstract: Digital transmission system (10) for digitally modulated signals, comprising a receiving device (14) which includes a demodulator (110), processing apparatus (120) and carrier synchronizing apparatus (16) for estimating and compensating for synchronization errors. The synchronizing apparatus includes a first loop (1) for phase/frequency correction and a second loop (2) for phase correction, the operation of these loops being controlled by a mode detector (130) depending on whether the receiving device is seeking to unlock or lock. The second loop (2) transforms a phase error signal into a phase correction signal which is mixed in mixer (246) with the signal coming from the demodulator. Preferably, the signals are modulated via a coded modulation.

Abstract: A bit synchronization circuit receives a first clock signal, a higher-frequency second clock signal, and digital data synchronized with the first clock signal. From the first clock signal, the circuit generates a write control signal that cyclically selects memory elements from a group of memory elements, and stores the digital data in the selected memory elements. From the second clock signal, the circuit generates a read control signal that cyclically selects memory elements from the same group, and outputs the digital data from the selected memory elements. The circuit also compares the phase of the read and write control signals, and adjusts the phase of the read control signal in response to the phase relation between the write control signal and read control signal.

Abstract: A bus transceiver in a first signal processing circuit is connected to one end of a first bus connecting line for transferring a data pulse signal. A bus transceiver in a second signal processing circuit is connected to one end of a second bus connecting line for transferring a data pulse signal. Connected to the other end of the first bus connecting line is a first termination resistor. Connected to the other end of the second bus connecting line is a second termination resistor. In a portion of a predetermined length (parallel coupling portion) in the first and second bus connecting lines, the interval between the first and second bus connecting lines is held substantially constant so as to produce capacitive and inductive coupling between both the bus connecting lines. Each of the first and second bus transceivers includes a bus driver and a bus receiver.

Abstract: A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

Abstract: A master and a slave digital frequency synthesizer are phase-locked such that the master synthesizer is always selected to minimize the phase hits which occur when switching the master to be a slave and vice versa. The switching rearrangement is done automatically and rapidly in the event of failure of the master frequency synthesizer.

Abstract: An apparatus for demodulating a phase modulation wave reduces an error rate of a demodulating circuit to perform a delay detection of an n-phase shift keying modulation wave without raising a clock frequency. When converting the received n-phase shift keying modulation wave into a rectangular wave, a waveform converting circuit for converting the n-phase shift keying modulation wave into a rectangular wave of a duty ratio which is larger or smaller than 50% is used. The rectangular wave is clocked through parallel registers of different lengths, outputs of the registers being operated on by exclusive-OR gates with the rectangular wave. Outputs of the gates are applied to respective one of a pair of counters, operated by a common clock signal, during periods of equality of outputs signals of the gates to provide a function of discriminating reproduction. A parallel/series converting circuit arranges upper bits and lower bits for reconstruction of each symbol of an original data message.

Abstract: A data output portion transmits a pulse signal having a pulse width according to a value of transmit data on a predetermined cycle. An H pulse width counter and an L pulse width counter measure a length of a high level period and a length of a low level period in the received pulse signal by using a clock signal having the same frequency as that of the clock signal used in the data output portion. A comparing portion compares the sum of both the measured lengths of the periods with the predetermined cycle, and outputs an error signal in case of a mismatch. In a PWM communication system, it is also possible to detect a signal delay or an error of the clock signal, which is temporarily caused within one cycle.

Abstract: The invention provides a synchronous circuit which prevents occurrence of a step-out condition even when an error in padding occurs. The synchronous circuit is applied to a digital transmission system wherein the number of bits in a frame varies periodically and bit number information is included in a frame. Making use of the fact that the bit number information has a periodicity, bit number information for one period is generated by a padding bit generator based on information from a synchronism detector to prevent occurrence of a step-out condition caused by an error in received bit number information.

Abstract: The present invention includes a method and system for controlling an equalizer equalizing data transmitted a communications channel which is oversampled at an oversampling rate of M. The method of the present invention includes the steps of initializing a plurality of data pointers and a first buffer stored in an input memory (22); generating a buffer full flag in response to filling the first buffer with a pre-determined number of data samples; initializing a counter (28) in response to the buffer full flag, the counter (28) generating an enable signal every M cycles; equalizing a portion of the pre-determined number of data samples in response to the enabling signal using an equalizer (20), where the portion of the pre-determined number of data samples is located using the plurality of data pointers; and adjusting the plurality of data pointers in response to the equalizing step using an FSE controller (24).