Patents Examined by Bo B Jang
  • Patent number: 11811013
    Abstract: A display panel includes a drive element, a first heat dissipation layer, a light-emitting element, and a second heat dissipation layer. The drive element is disposed on a substrate. The first heat dissipation layer is disposed on the drive element. The light-emitting element is disposed on the first heat dissipation layer and electrically connected to the drive element. The second heat dissipation layer covers the light-emitting element. A refractive index of the first heat dissipation layer is greater than a refractive index of the second heat dissipation layer when a light-emitting surface of the light-emitting element faces the first heat dissipation layer, and the refractive index of the second heat dissipation layer is greater than the refractive index of the first heat dissipation layer when the light-emitting surface of the light-emitting element faces the second heat dissipation layer.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: November 7, 2023
    Assignee: Au Optronics Corporation
    Inventors: Chun-Cheng Cheng, Chan-Jui Liu, Seok-Lyul Lee
  • Patent number: 11798927
    Abstract: A display device includes: a substrate including a pixel area; and a pixel in the pixel area, the pixel including a first sub-light emitting area, a second sub-light emitting area, and a peripheral area surrounding the first and second sub-light emitting areas. The pixel may include: a first electrode, a second electrode, a third electrode, and a fourth electrode that are spaced from each other; a plurality of light emitting elements in the first and second sub-light emitting areas; a bank in the peripheral area and including a first opening corresponding to the first sub-light emitting area and a second opening corresponding to the second sub-light emitting area; and an intermediate bank between the first sub-light emitting area and the second sub-light emitting area and partially overlapping the second and third electrodes in a plan view.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: October 24, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung Jae Yun, Sang Hoon Park, Jee Hoon Park, Dong Woo Shin, Hang Jae Lee, Jae Won Choi
  • Patent number: 11791285
    Abstract: A device includes an outer seal ring, an integrated circuit, and an inner seal ring. The outer seal ring forms a first closed loop. The integrated circuit is surrounded by the outer seal ring. The inner seal ring is between the outer seal ring and the integrated circuit. The inner seal ring forms a second closed loop that defines an enclosed region external to the integrated circuit.
    Type: Grant
    Filed: May 13, 2021
    Date of Patent: October 17, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Hui Yang, Chun-Ting Liao, Yi-Te Chen, Chen-Yuan Chen, Ho-Chun Liou
  • Patent number: 11791278
    Abstract: Provided are a display substrate motherboard and manufacturing method thereof, a display substrate and a display apparatus. The display substrate motherboard includes a substrate, a display substrate area on the substrate, and a mark area on the periphery of the display substrate area. The display substrate motherboard also includes a thin film transistor disposed in the display substrate area, a mark structure disposed in the mark area and a planarization layer disposed on one side of the thin film transistor away from the substrate, and the planarization layer includes a groove which is disposed at the corresponding position of the mark structure and extends along a direction close to the substrate, and an orthographic projection of the groove on the substrate covers an orthographic projection of the mark structure on the substrate.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: October 17, 2023
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Lei Yao, Feng Li, Lei Yan, Kai Li, Chenglong Wang, Teng Ye, Lin Hou, Xiaofang Li
  • Patent number: 11791418
    Abstract: Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: October 17, 2023
    Assignee: LG Display Co., Ltd.
    Inventors: SeungJin Kim, HeeSung Lee, Sohyung Lee, MinCheol Kim, JeongSuk Yang, JeeHo Park, Seoyeon Im
  • Patent number: 11776919
    Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yang-Che Chen, Victor Chiang Liang, Chen-Hua Lin, Chwen-Ming Liu, Huang-Wen Tseng
  • Patent number: 11764283
    Abstract: Disclosed is a semiconductor device including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate. The dielectric layer includes a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure, and an oxidation seed layer including an oxidation seed material. The oxidation seed material has a lattice constant having a lattice mismatch of 6% or less with one of a horizontal lattice constant and a vertical lattice constant of the hafnium oxide having the tetragonal crystal structure.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: September 19, 2023
    Inventors: Sunmin Moon, Young-Lim Park, Kyuho Cho, Hanjin Lim
  • Patent number: 11764168
    Abstract: A chip package structure is provided. The chip package structure includes a wiring substrate having a surface. The chip package structure includes a chip structure over the surface of the wiring substrate. The chip package structure includes an antiwarpage structure over the surface of the wiring substrate. The antiwarpage structure surrounds the chip structure. The chip package structure includes a first anchor structure affixed to the surface of the wiring substrate and adjacent to a first lower portion of the antiwarpage structure. The first lower portion is between the first anchor structure and the chip structure, and the first anchor structure is electrically isolated from the chip structure.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: September 19, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hui-Ting Lin, Chin-Fu Kao, Chen-Shien Chen
  • Patent number: 11749623
    Abstract: A method for fabricating memory devices includes forming a first portion of a memory device that includes a first device portion and one or more first interface portions. The first device portion includes a plurality of first memory strings, each of which includes a plurality of first memory cells vertically separated from one another. Each of the one or more first interface portions, laterally abutted to one side of the first device portion, includes a plurality of first word lines (WLs). The method further includes forming a plurality of first source lines (SLs) and a plurality of first bit lines (BLs) in the first device portion. The method further includes forming a first seal ring structure that laterally encloses both the first device portion and the first interface portion concurrently with forming the pluralities of SLs and BLs.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: September 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Han Lin, Chia-En Huang
  • Patent number: 11749691
    Abstract: An electronic device substrate, a manufacturing method thereof, and an electronic device are provided. The electronic device substrate includes a base substrate, a first insulating layer, and light-emitting sub-units, a first conductive member and a second conductive member, which are on a side of the first insulating layer away from the base substrate. The light-emitting sub-units and the first conductive member are respectively in array region and periphery region, and the second conductive member is between the first conductive member and the array region; orthogonal projections of the first and second conductive members on the base substrate are spaced apart; each light-emitting sub-unit includes first and second driving electrodes, second driving electrodes of the light-emitting sub-units are integrated to form a first common electrode layer; the periphery region further includes a second common electrode layer electrically connected to the first conductive member and the first common electrode layer.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: September 5, 2023
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Kui Zhang, Pengcheng Lu, Li Liu, Yunlong Li, Dacheng Zhang
  • Patent number: 11749658
    Abstract: A display device includes a substrate including a display area having a plurality of pixel areas and a non-display area located at at least one side of the display area; a pixel in each of the pixel areas; and a plurality of fan-out lines in the non-display area to form a first conductive layer. The pixel includes a pixel circuit layer including at least one transistor and a first bridge line and a second bridge line; and a display element layer on the pixel circuit layer. Each of the first and second bridge lines is electrically connected to a corresponding fan-out line from among the fan-out lines.
    Type: Grant
    Filed: June 16, 2022
    Date of Patent: September 5, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hye Lee, Kyung Bae Kim, Mee Hye Jung
  • Patent number: 11749620
    Abstract: A semiconductor module includes: a semiconductor element; and a sealing member. The semiconductor element includes: a semiconductor substrate; a protection film on the semiconductor substrate; a metal film on the semiconductor substrate and having at least a part located between the semiconductor substrate and the protection film; and a dummy metal film on the semiconductor substrate between the metal film and the protection film. The surface of the semiconductor substrate has a recess. The protection film has an other recess or a hole. The dummy metal film is arranged in both the recess of the semiconductor substrate and the other recess or the hole of the protection film.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: September 5, 2023
    Assignee: DENSO CORPORATION
    Inventor: Junji Tanaka
  • Patent number: 11749582
    Abstract: A package structure includes a bottom plate, a semiconductor package, a top plate, a screw and an anti-loosening coating. The semiconductor package is disposed over the bottom plate. The top plate is disposed over the semiconductor package, and includes an internal thread in a screw hole of the top plate. The screw penetrates through the bottom plate, the semiconductor package and the top plate, and includes an external thread. The external thread of the screw is engaged to the internal thread of the top plate, and the anti-loosening coating is adhered between the external thread and the internal thread.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: September 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Chen-Hua Yu, Chung-Shi Liu, Hsiao-Chung Liang, Hao-Yi Tsai, Chien-Ling Hwang, Kuo-Lung Pan, Pei-Hsuan Lee, Tin-Hao Kuo, Chih-Hsuan Tai
  • Patent number: 11742378
    Abstract: A light emitting diode (LED) may include a conductive via in a first portion of an epitaxial layer and a first contact on a second portion of the epitaxial layer. The first portion and the second portion may be separated by an isolation region. The LED may include a transparent conductive layer on the epitaxial layer.
    Type: Grant
    Filed: April 28, 2022
    Date of Patent: August 29, 2023
    Assignee: Lumileds LLC
    Inventors: Frederic Stephane Diana, Alan Andrew McReynolds
  • Patent number: 11742462
    Abstract: A method for manufacturing a display device includes: providing a plurality of light emitting elements on a substrate; providing a first photosensitive resin layer on the light emitting elements; driving a plurality of first light emitting elements among the plurality of light emitting elements, the driving of the plurality of first light emitting elements hardening a portion of the first photosensitive resin layer which corresponds to the plurality of first light emitting elements; and providing a first color converting layer as the portion of the first photosensitive resin layer which is hardened, by removing a remaining portion of the first photosensitive resin layer.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: August 29, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deukseok Chung, Shin Ae Jun
  • Patent number: 11742361
    Abstract: A display substrate, a method for manufacturing a display substrate and a display device are provided, and the display substrate includes: a base having a first surface, a second surface and a side surface, the base includes a display area and an epitaxial area; a driving functional layer in the display area and first binding electrodes in the epitaxial area on the first surface, the first binding electrodes are coupled with the driving functional layer; second binding electrodes located on the second surface and coupled with the first binding electrodes through side wirings; a portion of each side wiring is located on the side surface; a blocking wall on the first surface and in the epitaxial region, an orthographic projection of the blocking wall on the base at least passes through spacing regions between every two adjacent first binding electrodes along an arrangement direction of the first binding electrodes.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: August 29, 2023
    Assignees: BOE MLED TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Linhui Gong, Chao Liu
  • Patent number: 11735558
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: August 22, 2023
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Mohit Bhatia, Anurag Tripathi, Takeshi Nakazawa, Steve Cho
  • Patent number: 11728463
    Abstract: An image display device includes a plurality of pixels each of which includes a plurality of first subpixels and a second subpixel. The plurality of first subpixels is configured to emit red light, green light, and blue light. The second subpixel is configured to emit blue light. The plurality of pixels includes at least one pixel in which the plurality of first subpixels includes a defective subpixel which is supposed to emit predetermined light with a predetermined color. The second subpixel includes a light-emitting element and a wavelength conversion layer provided over the light-emitting element to convert emission light emitted from the light-emitting element to converted light with the predetermined color if the predetermined color is red or green.
    Type: Grant
    Filed: November 4, 2021
    Date of Patent: August 15, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Hajime Akimoto
  • Patent number: 11728329
    Abstract: A semiconductor device includes: a capacitor disposed over a substrate including a lower electrode, a dielectric layer, and an upper electrode; and a discharge structure spaced apart from the capacitor, connected to the upper electrode of the capacitor, and suitable for discharging, to the substrate, a charge induced from a plasma process for forming the upper electrode of the capacitor.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: August 15, 2023
    Assignee: SK hynix Inc.
    Inventor: Sang Yun Nam
  • Patent number: 11728371
    Abstract: An LED module includes light emission windows; LED cells corresponding to the light emission windows, the LED cells each including a lower and upper light emitting structure, the lower light emitting structure having an upper surface with first and second regions and having a first conductivity-type semiconductor layer, the upper light emitting structure being on the first region of the lower light emitting structure and having a second conductivity-type semiconductor layer, the LED cells including an active layer between the first and second conductivity-type semiconductor layers; a protective insulating film on a side surface of the lower light emitting structure and on the second region; a light blocking film on the protective insulating film, between the LED cells; a gap-fill insulating film on the protective insulating film between the LED cells and contacting a side surface of the upper light emitting structure; a first electrode; and a second electrode.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihye Yeon, Hanul Yoo, Jihoon Yun, Suhyun Jo