Abstract: A method and apparatus for providing support for voice communications and data communications at a base station which has a plurality of transceivers, each having a voice mode of operation and a data mode of operation, is disclosed. A first voice call is assigned to a first transceiver, wherein the mode of the transceiver is set to the voice mode of operation. A data transmission is assigned to a second available transceiver, wherein the mode of the transceiver is set to the data mode of operation. The data transmission is halted when a second voice call needs to be handled by the second transceiver. The mode of operation of the second transceiver is changed from the data mode to the voice mode and the second call is initiated. The data transmission is then assigned to the next available transceiver as long as a voice call does not need to be carried, wherein the mode of the transceiver is set to the data mode of operation.

Abstract: A method and a communications system in which a request for data transmitted by an airborne transmitter over a low-bandwidth air-to-ground communication system uplink and received by a ground-based receiver. The requested data is then transmitted over a high-bandwidth communication system downlink, such as a DBS satellite system downlink, preferably using an MPEG-2 compression technique, and received by an airborne receiver located on the same aircraft as the airborne transmitter. The received request for data is transmitted to a data network that contains the requested data, such as the Internet or a private data network, using circuit-switched techniques. According to the invention, the requested data includes one of video information, audio information and textual information.

Abstract: According to the present disclosure, an parallel formatted data signal is applied to an input (300), and the data signal is divided into a first data signal and a second data signal. The second data signal is applied to a logic delay element (606) to produce a delayed second data signal that is a delayed-in-time version of the first data signal. The first data signal is applied to a first parallel-to-serial converter (706), the delayed second signal is applied to a second parallel-to-serial converter (708), and first and second bit-serial data streams are produced. A controller (710) synchronizes an Arithmetic Logic Unit (616) to the first and second bit-serial data streams so that the ALU (616) scales and sums the first and second bit-serial data streams to produce a bit-serial, sample-rate converted, output signal.