Patents Examined by Bradley William Baumeister
  • Patent number: 6878975
    Abstract: A novel tunnel structure is described that enables tunnel diode behavior to be exhibited even in material systems in which extremely heavy doping is impossible and only moderate or light doping levels may be achieved. In one aspect, the tunnel heterostructure includes a first semiconductor layer, a second semiconductor layer, and an intermediate semiconductor layer that is sandwiched between the first and second semiconductor layers and forms first and second heterointerfaces respectively therewith. The first and second heterointerfaces are characterized by respective polarization charge regions that produce a polarization field across the intermediate semiconductor layer that promotes charge carrier tunneling through the intermediate semiconductor layer. In another aspect, the invention features a semiconductor structure having a p-type region, and the above-described heterostructure disposed as a tunnel contact between the p-type region of the semiconductor structure and an adjacent n-type region.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: April 12, 2005
    Assignee: Agilent Technologies, Inc.
    Inventor: Mark R. Hueschen
  • Patent number: 6867439
    Abstract: A high electron mobility transistor using a Group III-V compound semiconductor comprises an undoped second channel layer laminated on an InP substrate via a buffer layer, an undoped first channel layer laminated on the second channel layer, and a doped electron-supplying layer laminated on the first channel layer. The first channel layer is composed of In1-xGaxAs and has an energy level of conduction band lower than that of the electron-supplying layer at the interface. The second channel layer is composed of a Group III-V compound semiconductor using a Group V element other than P, has an energy level of conduction band higher than that of the first channel layer, and has a band gap wider than that of the first channel layer.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Limited
    Inventor: Kenji Imanishi
  • Patent number: 6642537
    Abstract: A quantum well infrared photodetector (QWIP) that provides two-color image sensing. Two different quantum wells are configured to absorb two different wavelengths. The QWIPs are arrayed in a focal plane array (FPA). The two-color QWIPs are selected for readout by selective electrical contact with the two different QWIPs or by the use of two different wavelength sensitive gratings.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: November 4, 2003
    Assignee: California Institute of Technology
    Inventors: Sarath D. Gunapala, Kwong Kit Choi, Sumith V. Bandara
  • Patent number: 6639255
    Abstract: A semiconductor device includes: a substrate; a buffer layer including GaN formed on the substrate, wherein: surfaces of the buffer layer are c facets of Ga atoms; a channel layer including GaN or InGaN formed on the buffer layer, wherein: surfaces of the channel layer are c facets of Ga or In atoms; an electron donor layer including AlGaN formed on the channel layer, wherein: surfaces of the electron donor layer are c facets of Al or Ga atoms; a source electrode and a drain electrode formed on the electron donor layer; a cap layer including GaN or InGaAlN formed between the source electrode and the drain electrode, wherein: surfaces of the cap layer are c facets of Ga or In atoms and at least a portion of the cap layer is in contact with the electron donor layer; and a gate electrode formed at least a portion of which is in contact with the cap layer.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: October 28, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kaoru Inoue, Katsunori Nishii, Hiroyuki Masato
  • Patent number: 6635950
    Abstract: To improve the gettering performance by ion implanting boron and improves the production yield of the semiconductor device by using an epitaxial wafer of good quality suppressing the occurrence of dislocations. For this purpose, an epitaxial wafer in which an epitaxial layer of about 1 &mgr;m is formed to a CZ semiconductor substrate implanted with boron ions which are dopant and carbon ions which are not a dopant is provided, and transistors are formed on the surface of the epitaxial layer.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: October 21, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hidetsugu Ishida, Seiichi Isomae
  • Patent number: 6630695
    Abstract: A GaN based three layer buffer structure disposed on a substrate, and having a GaN layer disposed on the three layer buffer structure, the GaN layer serving as a platform for growth of a light emitting structure thereon.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: October 7, 2003
    Inventors: Changhua Chen, James Dong, Heng Liu
  • Patent number: 6528828
    Abstract: A differential negative resistance element includes a heavily doped GaAs layer interposed between a collector layer of lightly doped GaAs and an emitter layer of heavily doped AlGaAs, is shared between a base region between the collector layer and the emitter layer, a base contact region and a channel region between the base region and the base contact region, and a depletion layer is developed into the channel region together with the collector voltage so as to exhibit a differential negative resistance characteristics, wherein the channel region is formed through an epitaxial growth and etching so that the manufacturer easily imparts target differential negative resistance characteristics to the channel region.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: March 4, 2003
    Assignee: NEC Corporation
    Inventor: Tetsuya Uemura
  • Patent number: 6495867
    Abstract: A GaN based three layer buffer on a sapphire substrate provides a template for growth of a high quality I GaN layer as a substitute substrate for growth of a Nitride based LED.
    Type: Grant
    Filed: July 26, 2000
    Date of Patent: December 17, 2002
    Assignee: AXT, Inc.
    Inventors: Changhua Chen, James Dong, Heng Liu
  • Patent number: 6486490
    Abstract: An emission layer is formed in a p-layer, and an electron reflecting layer and a hole reflecting layer are formed sandwiching the emission layer. Each of the electron reflecting layer and the hole reflecting layer is constituted by a quantum-wave interference layer with plural periods of a pair of a first layer W and a second layer B. Thicknesses of the first and the second layers in the electron reflecting layer are determined by multiplying by an odd number one fourth of a quantum-wave wavelength of electrons in each of the first and the second layers, and each thicknesses of the first and the second layers in the hole reflecting layer are determined by multiplying by an odd number one fourth of a quantum-wave wavelength of holes in each of the first and the second layers. A luminous efficiency of the LED is improved by electron-hole pairs.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: November 26, 2002
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6433355
    Abstract: An organic light emitting device is provided having a substrate (60), an anode contact electrode (64), a cathode contact electrode (61), and an organic region (62, 63) in which electroluminescence takes place if a voltage is applied between the anode (64) and cathode (61). At least one of the electrodes (61, 64) comprises a non-degenerate wide bandgap semiconductor.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Walter Riess, Samuel C. Strite
  • Patent number: 6420727
    Abstract: A light-emitting device comprising an emission layer which has a single layer structure is formed. The emission layer is sandwiched by a first quantum-wave interference layer constituted by plural periods of a pair of a first layer and a second layer, the second layer having a wider band gap than the first layer, and a second quantum-wave interference layer constituted by plural periods of a pair of a third layer and a fourth layer, the fourth layer having a wider band gap than the third layer. The first quantum-wave interference layer functions as an electron reflection layer, and its thickness is determined by multiplying by an odd number one fourth of quantum-wave wavelength of the injected electrons. The second quantum-wave interference layer functions as an electron transmission layer, and its thickness is determined by multiplying by an odd number one fourth of quantum-wave wavelength of the injected electrons. As a result, luminous efficiency of the device is improved.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: July 16, 2002
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6420726
    Abstract: A triode field emission device using a field emission material and a driving method thereof are provided. In this device, gate electrodes serving to take electrons out of a field emission material on cathodes are installed on a substrate below the cathodes, so that the manufacture of the device is easy. Also, electrons emitted from the field emission material are controlled by controlling gate voltage.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: July 16, 2002
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Yong-soo Choi, Jun-hee Choi, Nae-sung Lee, Jong-min Kim
  • Patent number: 6417520
    Abstract: A light-emitting diode comprising a quantum-wave reflection layer for electrons, a quantum-wave transmission layer for electrons, and an emission layer formed between the quantum-wave reflection layer and th e quantum-wave transmission layer is used as a photocoupler. Compared with a commercial product having a response velocity of 20 MHz, a response velocity of the light-emitting diode of the present invention is improved to be 100 MHz to 200 MHz. The quantum-wave reflection layer for electrons and the quantum-wave transmission layer for electrons are formed to have thicknesses of one fourth and a half of quantum wave of electrons, respectively.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: July 9, 2002
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6399971
    Abstract: The semiconductor device comprises a collector layer 14; a base layer 16 of a carbon-doped GaxIn1−xAsySb1−y layer having one surface connected to the collector layer 14; an emitter layer 18 connected the other surface of the base layer 16; a base contact layer 30 of a carbon-doped GaAsSb layer electrically connected to the base layer 16; and a base electrode 32 formed on the base contact layer 30. The semiconductor device of such structure can have a much reduced base resistance RB, whereby InP/GaInAsSb-based HBTs including InP/InGaAs-based HBTs can have higher maximum oscillation frequency fmax. Because of the carbon-doped semiconductor layer the semiconductor device can have higher reliability.
    Type: Grant
    Filed: November 13, 1998
    Date of Patent: June 4, 2002
    Assignee: Fujitsu Limited
    Inventors: Hisao Shigematsu, Kenji Imanishi, Hitoshi Tanaka
  • Patent number: 6399970
    Abstract: Si and SiGeC layers are formed in an NMOS transistor on a Si substrate. A carrier accumulation layer is formed with the use of a discontinuous portion of a conduction band present at the heterointerface between the SiGeC and Si layers. Electrons travel in this carrier accumulation layer serving as a channel. In the SiGeC layer, the electron mobility is greater than in silicon, thus increasing the NMOS transistor in operational speed. In a PMOS transistor, a channel in which positive holes travel, is formed with the use of a discontinuous portion of a valence band at the interface between the SiGe and Si layers. In the SiGe layer, too, the positive hole mobility is greater than in the Si layer, thus increasing the PMOS transistor in operational speed. There can be provided a semiconductor device having field-effect transistors having channels lessened in crystal defect.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: June 4, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kubo, Katsuya Nozawa, Masakatsu Suzuki, Takeshi Uenoyama, Yasuhito Kumabuchi
  • Patent number: 6310385
    Abstract: An integrated circuit is provided in which a relatively low band gap material is used as a semiconductor device layer and in which an underlying high (wide) band gap material is used as an insulating layer. The insulating material has a high thermal conductivity to allow heat dissipation in conjunction with dielectric isolation. The integrated circuit includes one or more semiconductor wells which are each surrounded on their sides by an insulating material. The bottom of the semiconductor wells are disposed atop the high band gap material which provides both electrical isolation and thermal conductivity. A semiconductor substrate may be provided to support the high band gap material. A layer of insulating material may also be provided between the high band gap material and the semiconductor substrate.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: October 30, 2001
    Assignee: International Rectifier Corp.
    Inventor: Janardhanan S. Ajit
  • Patent number: 6294795
    Abstract: A light-receiving device of a pin junction structure, constituted by a quantum-wave interference layers Q1 to Q4 with plural periods of a pair of a first layer W and a second layer B and carrier accumulation layers C1 to C3. The second layer B has wider band gap than the first layer W. Each thicknesses of the first layer W and the second layer B is determined by multiplying by an odd number one fourth of wavelength of quantum-wave of carriers in each of the first layer W and the second layer B existing at the level near the lowest energy level of the second layer B. A &dgr; layer, for sharply varying energy band, is formed at an every interface between the first layer W and the second layer B and has a thickness substantially thinner than the first layer W and the second layer B. As a result, when electrons are excited in the carrier accumulation layers C1 to C3, electrons are propagated through the quantum-wave interference layer from the n-layer to the p-layer as a wave, and electric current flows rapidly.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: September 25, 2001
    Assignee: Canare Electric Co., Ltd.
    Inventor: Hiroyuki Kano
  • Patent number: 6285269
    Abstract: A drain electrode and a source electrode are provided for an intrinsic device section on a GaAs substrate with a gate electrode placed therebetween. Almost all or substantial parts of the GaAs substrate is covered by an extending source electrode extending from the source electrode. A belt-shaped extending drain electrode is provided on the extending source electrode with a dielectric layer placed therebetween, and thereby an output-side microstripline is formed. A belt-shaped extending gate electrode is also provided on the extending source electrode with a dielectric layer placed therebetween, and thereby an input-side microstripline is formed.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: September 4, 2001
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yohei Ishikawa, Koichi Sakamoto, Sadao Yamashita, Takehisa Kajikawa
  • Patent number: 6218677
    Abstract: A resonant tunneling diode (400) made of a quantum well (406) with tunneling barriers (404, 408) made of two different materials such as calcium fluoride (408) and silicon dioxide (404). The calcium fluoride provides lattice match between the emitter (410) and the quantum well (406). Further resonant tunneling diodes with silicon lattice match barriers may be made of III-V compounds containing nitrogen.
    Type: Grant
    Filed: August 15, 1994
    Date of Patent: April 17, 2001
    Assignee: Texas Instruments Incorporated
    Inventor: Tom P. E. Broekaert
  • Patent number: 6204513
    Abstract: A heterostructure interband tunneling diode includes a contact layer comprising indium gallium arsenide of a first conductivity type, an injection layer comprising indium gallium arsenide of a second conductivity type, a first doped layer of the first conductivity type positioned adjacent to the contact layer, and a second doped layer of a second conductivity type juxtaposed between the first doped layer and the injection layer, wherein at least one of the first and second tunnel barrier layers comprises indium aluminium arsenide. A second embodiment includes a doped layer of the first conductivity type positioned adjacent to the contact layer, and a barrier layer positioned adjacent to the injection layer, and a quantum well layer comprising indium gallium arsenide juxtaposed between the doped layer and the barrier layer, wherein at least one of the doped and barrier layers comprises indium aluminium arsenide.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: March 20, 2001
    Assignee: Motorola, Inc.
    Inventors: Nada El-Zein, Jonathan Lewis, Mandar R. Deshpande