Abstract: A method of designing an integrated circuit (IC) device includes identifying, with a processor, a pin failing a test to determine an antenna effect, identifying, with the processor, a net corresponding to the identified pin failing the test to determine the antenna effect, and creating, with the processor, an engineering change order (ECO) script based on the identified net to insert a diode to address the antenna effect.

Abstract: The disclosure provides a system to simulate a simulated noise on the power zone block of a substrate. The system comprises a signal trace and a signal generating circuit. The signal trace is disposed adjacent to the power zone block. The signal generating circuit is electrically coupled to the signal trace, configured to transmit an alternating current signal over the signal trace. The alternating current signal transmitted over the signal trace is configured to induce a simulated noise on the power zone block, and a waveform of the simulated noise is determined by a frequency of the alternating current signal.

Abstract: This application provides a battery protection circuit, a battery protection board, a battery, and a terminal device. The battery protection circuit includes: a first detection unit; a second detection unit; and a current detection element, a first switch unit, and a second switch unit that are configured to connect to an electrochemical cell in series, to form a charging loop or a discharging loop. The first detection unit corresponds to the first switch unit, and the second detection unit corresponds to the second switch unit. Each detection unit controls, based on a detected voltage at two ends of the same current detection element, a corresponding switch unit to be closed or opened, so as to control the loop to be closed or opened.

Abstract: A chip includes a first circuitry and a second circuitry. The first circuitry includes first circuits which have first power consumption at a point of time. The second circuitry includes second circuits which have second power consumption at the point of time, and the first power consumption is higher than the second power consumption. At least one of the first circuits and at least one the second circuits are alternately arranged, in order to lower an operating temperature of the plurality of first circuits at the point of time.

Abstract: A method for dynamically generating or interacting with an electromagnetic field includes providing a spatial array of conductive segments, a switching device operable on each of the conductive segments to either allow or block transmission of an electrical signal and a control device operable on the switching device. A sequence of the conductive segments are connected to form a conductive path where each segments intersects with at least two different ones of the conductive segments at a node. The switching device operates to connect a selected first one of the conductive segments with a selected second one of the conductive segments to form the sequence according to a logic signal from the control device. Power is supplied to the conductive path to produce an electromagnetic field which depends at least in part on the spatial arrangement of the connected sequence of the conductive segments.

Abstract: A computer design verification system comprising a parsing module configured to receive output messages from a computer design testing tool and to compose from the output messages formatted objects comprising a set of fields having field descriptors and test values; a signoff module holding a plurality of signoff objects, each comprising a plurality of fields having a field descriptor, at least some fields populated with a signoff expression, each signoff object associated with a severity level indicative of the severity of a condition represented by the signoff object. The signoff module is configured compare at least one test value in the formatted objects received from the parsing module with at least one signoff expression in the signoff objects to determine if a signoff object matches the formatted object, and in the case of a match, associating the severity level of the signoff object with the formatted object.

Abstract: The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal.

Abstract: Systems and methods are described herein for attribute-point-based timing formal verification of application specific integrated circuit (ASIC) and system on chip (SoC) designs. A target circuit design having a first set of netlists and timing constraints is received. A plurality of key clock-pin-net-load-setting attributes are extracted from the first ported netlists and timing constraints. The clock-pin-net-load-setting attribute mismatch in the result report is checked between the target circuit design and a golden circuit design by comparing the plurality of target attributes with a plurality of golden attributes of the golden circuit design after the target design database is loaded for static timing analysis (STA).

Abstract: Various embodiments include modeling a component fault tree for a circuit with an input-side and an output-side component. These include using a fault tree corresponding to a hazard for each respective component, obtaining information about the components of the circuit and a connection between components, and connecting the respective fault trees based on the circuit description. Each fault tree includes an input fault mode or a basic event and an output fault mode. The output fault mode and the input fault mode are each assigned to a component terminal. An output fault mode of the input-side component tree is connected to an input fault mode of the output-side component tree if: there is a connection between the assigned terminal of the input-side component and the output-side component and the output fault mode of the input-side component correlates to an input fault mode of the output-side component.

Abstract: Systems and methods for generating defect criticality are disclosed. Such systems and methods may include identifying defect results including a defect and a defect location. Such systems and methods may include receiving fault test recipes configured to test potential faults at a plurality of testing locations. Such systems and methods may include identifying a plurality of N-detect parameters based on a countable number of times the fault test recipes are configured to test a potential fault. Such systems and methods may include determining a plurality of weighting parameters based on the plurality of N-detect parameters. Such systems and methods may include generating the defect criticality for the defect based on a proximity between the plurality of testing locations and the defect location and the plurality of weighting.

Abstract: Disclosed are a method for verifying a convolutional neural network model and a device thereof. The method for verifying the convolutional neural network model includes (a) generating a polynomial circuit equation for a first configuration of a plurality of configurations configuring the convolutional neural network model; (b) generating a first commitment value and a first proof value by applying a zero-knowledge proof scheme based on the polynomial circuit equation; (c) generating an arithmetic circuit equation for a second configuration of the plurality of configurations; (d) generating a second commitment value and a second proof value by applying a zero-knowledge proof scheme based on the arithmetic circuit equation; and (e) generating a connection proof value connecting the first commitment value and the second commitment value.

Abstract: A device and a method for integrated circuit assistance design, and a method for constructing an electrical performance gradient model are provided. The device includes a database and a processor. The database has an electrical performance gradient model. The electrical performance gradient model represents a gradient distribution of an electrical performance in a wafer. The processor is coupled to the database. The processor analyzes a designed circuit by using the electrical performance gradient model.

Abstract: A method for analyzing disaster prevention and mitigation effectiveness of an ecological seawall is provided, including: performing seawall ecologicalization on a target seawall; establishing three-dimensional space hydrodynamic force for the target ecological seawall; simulating wave climbing on a dike body and a wave overtopping on a dike top of the target ecological seawall to obtain a wave overtopping index; calculating wave-flow bottom shear stress of the target ecological seawall, establishing a sediment movement model, and calculating suspended load and bed load sediment transportation volumes; calculating the change index of coastal bed surface according to the suspended load and bed load sediment transportation volumes, and determining a development index of tidal flats in front of dike of the target ecological seawall according to the change index; and calculating the disaster prevention and mitigation effectiveness grade of the target ecological seawall according to the wave overtopping index and t

Abstract: A method for designing a circuit includes adding, to a circuit design, a power switch configured to produce only one output over an acknowledgement port. The power switch does not include input and output supply ports. The method also includes adding, to the circuit design, an isolation circuit in which only one select pin is used to produce an output. The isolation circuit does not include isolation power and retention circuitry. The method also includes adding, to the circuit design, a retention circuit. The retention circuit includes a clock gating enabled register, a first AND gate connected to a clear pin of the register, and a second AND gate connected to a chip enable pin of the register. The method further includes compiling, by a processing device, the circuit design.

Abstract: Vacant areas of a layer of an integrated circuit design are filled with shapes connected to the appropriate nets.

Abstract: Methods for generation of shape data for a set of electronic designs include inputting a set of shape data, where the set of shape data represents a set of shapes for a device fabrication process. A convolutional neural network is used on the set of shape data to determine a set of generated shape data, where the convolutional neural network comprises a generator trained with a pre-determined set of discriminators. The set of generated shape data comprises a scanning electron microscope (SEM) image.

Abstract: A routing assembly for an electronic device has a plurality of connectors ports and each of the connector ports contains a first connector connected to one or more cables. Cables are directly terminated, at first ends thereof, to terminals of the first connectors and the cables can be embedded in a routing substrate. The routing substrate has an opening which accommodates a chip package. Second ends of the cables are terminated to second connectors arranged in the package opening and the second connectors are in turn connected to the chip package.

Abstract: A method includes: receiving value changes corresponding to timestamped logic value changes in recorded signals from a verification run of an integrated circuit (IC) design; generating recorded logic vectors from the value changes, each of the recorded logic vectors being associated with a corresponding signal identifier, each of the recorded logic vectors including a recorded logic values over a window of consecutive clock cycles computed from one or more value changes associated with the corresponding signal identifier and having timestamps within the window of consecutive clock cycles; determining, by a processor, inferred logic vectors including inferred logic values corresponding to signals output by cells of the IC design based on propagating the recorded logic values of the recorded logic vectors through the cells; and computing per-cycle power characteristics of the IC design based on the recorded logic vectors and the inferred logic vectors.

Abstract: A system and method for the automatic placement of superconducting devices determines an arrangement of a series of Josephson junctions between a start point and an end point of an inductive wiring run on a superconducting circuit layout having a plurality of discrete Josephson junction placement sites by determining costs of placing each Josephson junction of the series of Josephson junctions at the plurality of discrete Josephson junction placement sites between the start point and the end point of the inductive wiring run based at least on a comparison of a target inductance value to inductances of wires connecting to the Josephson junction and selecting sites from the plurality of discrete Josephson junction placement sites to place each Josephson junction corresponding to the arrangement of the series of Josephson junctions with the least determined cost for the inductive wiring run.

Abstract: A method for boundary port modelling that correctly handles back-to-back isolation intent, level shifter intent and voltage level association, by providing hard association of power domains to soft data objects, such as wires. The method includes identifying a boundary port in a detailed power intent (DPI) for a soft design object (SDO). A non-wire object is inserted in the SDO for the boundary port. In the DPI, a power domain of the boundary port is assigned to the non-wire object.