Abstract: Integrated circuits and fabrication methods incorporating both two-terminal devices such as IMPATT diodes (446) and Schottky diodes (454) and three-terminal devices such as n-channel MESFETs (480) in a monolithic integrated circuit.

Abstract: An integrated circuit fabrication method begins with semiconductor devices formed on a substrate. A patterned metal layer is deposited on the substrate to connect the semiconductor devices. A nitride layer is deposited over the metal layer and substrate. The nitride layer topography comprises hills located over metal regions and valleys located over non-metal regions. Spin-on-glass (SOG) is deposited over the nitride layer, thereby filling the valleys and covering the hills. The SOG layer and the nitride layer hills are etched back at substantially the same etch rate, using plasma etching, to form a planar surface. An oxide layer is then deposited over the planar surface to encapsulate the semiconductor devices, metal layer, nitride layer and SOG layer. Vias may then be etched through the oxide layer and the nitride layer to expose portions of the underlying metal layer and facilitate upper layer metal connections thereto.

Abstract: For manufacturing an insulation trench in a SOI substrate wherein logic components and high-voltage power components are integrated, a trench extending down onto the insulating layer of the SOI substrate is etched. By providing the sidewalls of the trench with an occupation layer containing a dopant and by drive-out from the occupation layer, diffusion regions neighboring the trench are produced. After complete removal of the occupation layer, a silicon layer is produced and an insulation structure is formed in the trench by thermal oxidation.

Abstract: An integrated circuit (IC) device comprises towers of bonded gold balls located on each bond pad. The towers allow for early encapsulation of the IC die. The IC can then be tested and attached to tab tape or a printed circuit board without particulate contamination concerns.

Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal .portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.

Abstract: A method is provided for creating solder connections between two surfaces which connections are relatively weak and thus can be readily fractured for separating the surfaces. The preferred application of the disclosed process is its use in connecting semiconductor chips to a carrier in order to conduct burn-in tests on the chips. The process consists of a series of steps to form a surface having a matrix of solder wettable and solder non-wettable areas on the pads of the carrier. Once the solder balls on the chip are attached to the treated pads on the carrier, electrical contacts are made and the chip can be readily removed after the test. The uniquely configured carrier can then be reused numerous times for testing or burning-in chips.

Abstract: A method of forming a semiconductor-on-insulator (SOI) electronic device includes the steps of etching a semiconductor substrate to form a plurality of adjacent trenches therein and then forming electrically insulating layers on bottoms of the trenches. Epitaxial lateral overgrowth (ELO) is then performed to grow respective monocrystalline semiconducting regions in the trenches. These semiconducting regions are preferably grown from a sidewall of each trench onto a respective insulating layer and fill each trench. Monocrystalline active regions of the electronic device are then formed in the semiconducting regions and also in the substrate, adjacent the trench sidewalls. For example, a monocrystalline trench isolated extrinsic base region of a bipolar junction transistor (BJT) can be formed in a semiconducting region in a respective trench, and a corresponding intrinsic base region and an intrinsic collector region can be formed in the substrate, adjacent the semiconducting region.

Abstract: A single-etch stop process for the manufacture of silicon-on-insulator substrates. The process includes forming a silicon-on-insulator bonded substrate comprising a handle wafer, a device wafer, a device layer having a thickness of between about 0.5 and 50 micrometers, and an oxide layer with the device layer being between the device wafer and the oxide layer and the oxide layer being between the device layer and the handle wafer, the device wafer having a boron concentration of at least about 1.times.10.sup.18 boron atoms/cm.sup.3 and a resistivity of about 0.01 to about 0.02 ohm-cm. A portion of the device wafer is mechanically removed from the silicon-on-insulator bonded substrate wherein the device wafer has a total thickness variation across the surface of the wafer of less than about 2 micrometers and a defect-free surface after the mechanical removal step.

Abstract: A low dielectric constant insulation layer for an integrated circuit structure material, and a method of making same. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The porous insulation layer is formed by depositing a composite layer comprising an insulation material or a material which can be converted to an insulation material, by a converting process and a material which can be converted to a gas upon subjection to the converting process. Release of the gas leaves behind a porous matrix of the insulation material which has a lower dielectric constant than the composite layer.

Abstract: Optoelectronic semiconductor device comprising a waveguide and method of manufacturing such a device. Optoelectronic semiconductor devices which have a groove-shaped waveguide in an oxide layer provided on a silicon substrate are compact, easy to manufacture, and--when the waveguide comprises a non-linear optical material--applicable inter alia for frequency doubling of laser radiation. In known devices, scattering losses occur in the waveguide owing to the roughness of the groove which arises during etching of the groove. Here the groove and a portion of the oxide layer are formed by local, preferably thermal, oxidation of the silicon substrate. The groove formed at the area of the oxidation mask has a smoother surface and as a result the waveguide has lower losses. When the device includes a GaAs/AlGaAs diode laser, it forms an efficient, compact, inexpensive and blue-emitting laser source which is suitable for use in an optical disc system.

Abstract: In order to provide a process for applying structured layers of a functional structure of a semiconductor component, with which structured layers of a functional structure of a semiconductor component can be produced as simply as possible and with as little susceptibility as possible with respect to the quality of the semiconductor components, it is suggested that a material film be arranged above a surface region of a process substrate to be provided with the structured layer, that the material film be acted upon on its side remote from the process substrate by a focus of a laser beam located in a defined position corresponding to the structured layer to be produced and that with the laser beam in the region of the focus the material from the material film migrate to the surface region.

Abstract: A vacuum processing method including the steps of generating plasma of a charge neutralizing medium by plasma generating means in a vacuum process chamber, and supplying the charge neutralizing medium in the plasma state to an object during transportion in the vacuum process chamber, thereby neutralizing a charge on the object. With this method, the object can be smoothly transported in a vacuum atmosphere after treatment and adhesion of particles to the object is prevented.

Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.

Abstract: Method of fabricating a semiconductor device. A glass substrate such as Corning 7059 is used as a substrate. A bottom film is formed. Then, the substrate is annealed above the strain point of the glass substrate. The substrate is then slowly cooled below the strain point. Thereafter, a silicon film is formed, and a TFT is formed. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps. This makes it easy to perform mask alignments. Furthermore, defects due to misalignment of masks are reduced, and the production yield is enhanced. In another method, a glass substrate made of Corning 7059 is also used as a substrate. The substrate is annealed above the strain point. Then, the substrate is rapidly cooled below the strain point. Thereafter, a bottom film is formed, and a TFT is fabricated. The aforementioned anneal and slow cooling reduce shrinkage of the substrate created in later thermal treatment steps.

Abstract: Conductive bumps (24) are formed on a semiconductor device (10) by applying or depositing an imageable conductive layer (18) over the device and in contact with I/O pads of a final metallization layer (14). The imageable conductive material is formed of an imageable acrylic resin system filled with conductive particles. In one embodiment, a mask (20) having a pattern of transparent material (21) corresponding to the desired patterned of conductive bumps is used to expose the imageable conductive layer to radiation (23). The imageable conductive layer is then developed, thereby removing unexposed portions of the layer and leaving a plurality of conductive bumps (24) on the I/O pads of the device. Rather than using a negatively imaged conductive layer, a positive resin could be used in formulating the imageable conductive material.

Abstract: A structure and process for forming a contact to a semiconductor substrate on a semiconductor device comprises the step of forming a patterned mask over a semiconductor substrate and over a field oxide region, then etching the semiconductor substrate and the field oxide region to form a trench. The trench comprises a bottom and a first sidewall consisting of silicon and a second sidewall comprising field oxide. The etching step removes a part of a doped region in the substrate. Next, a blanket nitride layer and a blanket oxide layer is formed over the substrate, and a spacer etch is performed on the nitride and oxide layer leaving nitride and oxide over the first and second sidewalls. The trench bottom is oxidized to form a layer of oxide over the bottom of the trench thereby insulating the trench bottom, and the oxide encroaches under the nitride and oxide on the sidewalls to join with the field oxide.

Abstract: A substrate subassembly for a high power module, and methods involving the same. The substrate subassembly contains only one switching transistor and has at least one integral short terminal lead tab. The substrate subassemblies can be pretested at significant operating current, to obtain enhanced characterization and matching of mounted switching transistors. Trimmable gate lead resistances can be incorporated in the substrate subassemblies. Enhanced compositional, geometrical and electrical module symmetry is available. New module structures and method are afforded.

Abstract: An improved metal semiconductor package is described. The semiconductor package includes a lead frame with a top side and a bottom side. A semiconductor is positioned on the top side of the lead frame. Bond wires electrically couple the lead frame to the semiconductor die. A metallic base is positioned at the bottom side of the lead frame. A metallic cap is positioned over the top side of the lead frame. The metallic cap includes a central aperture that is aligned with the semiconductor die. An external plastic seal is used to join the metallic base, lead frame, and metallic cap. The external plastic seal may be in the form of a perimeter seal or a body seal.

Abstract: A method of forming a MOS device having a localized anti-punchthrough region, which is adjacent to but is not in contact with source/drain regions of the MOS device. A trench is formed by depositing a conducting layer on an oxide layer located on a channel region of the MOS device. The trench is used as a self-alignment mask for a subsequent implantation process to form the localized anti-punchthrough region.

Abstract: A method for forming contacts for establishing an electrical connection with contact locations on a semiconductor die is provided. The contacts are formed as raised members mounted on a compliant substrate. Each contact includes a rough textured surface having asperities adapted to penetrate the contact location on the die to a limited penetration depth. The height of the asperities is between about 1000.ANG. to 10,000.ANG.. The textured surface and asperities are formed by electroplating a rough metal layer on a raised metal contact or by etching a surface of a raised metal contact. In an illustrative embodiment the contacts comprise microbumps formed on a compliant polyimide substrate. For forming an interconnect suitable for establishing a temporary electrical connection with an unpackaged semiconductor die, the polyimide substrate is attached to a rigid substrate, such as silicon, having a coefficient of thermal expansion that matches that of a silicon die.