Abstract: Cache memory having pseudo virtual addressing, in which the addressing is performed by using the "offset" field of a current address and a physical address field of an address previously used and stored in a first register, and where, for each logical current address a comparison is made between the logical page addresses of the current address and that of the last used physical address which is stored in a second register. Along with the requested information the cache memory outputs, if available, the effective physical page address of the information, which is compared with the physical page address used for addressing and stored in the first register. In this way, the addressing is performed by physical addresses but without need to wait for translation of a virtual/logical address into a physical address.

Abstract: An external clock unit for use with a DEC MICROVAX model 31 computer includes a first crystal oscillator for generating a clock signal of about 44 MHZ, a second crystal oscillator for generating a clock signal of about 63 MHZ, a 2 to 1 multiplexor for receiving 44 MHZ clock signal and the 63 MHZ clock signal and outputting one of clock signals, a first switch for selecting which of the two clock signals is to be outputted by the 2 to 1 multiplexor, a second switch for selecting which one of two logic signals is to be outputted by a system identification code generator in the computer and a power supply for providing power to the device. In use, the external clock unit is connected to jumper pins on the processor clock signal line and the system identification code generator.

Abstract: A method for dispatching work requests in a data storage hierarchy in which directory data is promoted in variable length spans, the use of which are maximized even for work requests entering the work request queue after the span is chosen, is disclosed. A queue of work requests is initially scanned to determine if any requests therein require access to directory data stored in secondary storage within a prescribed proximity of that required by the next request to be dispatched. If such other work requests exist, then directory data in addition to that required by the next request to be dispatched is also promoted. To minimize seek time and rotational latency, the additional data is promoted from secondary storage in a single device I/O cycle. The additional data is chosen by adjusting the outer limits of the span as each work request in queue is scanned. After the actual promotion of the span of data, the existing work request is completed.

Abstract: The bit streams, transporting the frames, received from lines (6) are placed in register 12 in such a way that n bits are processed in parallel during a time interval T. Parallel processor 10 counts the consecutive logical "1" bits beginning at the low order (left most) bit of the n bits received in interval T and from the bits received in the previous interval T-1, to determine when this number is found equal to 5 which bits have to be deleted, and when this number is found equal to 6 whether a flag is received. As a result, it reassembles N-bit characters, with N<n, in register (16). The frame characters to be sent on lines (6) are stored into register (28), and processed in parallel in a time interval T by processor 10 which inserts 0 after five consecutive logical "1's" as a function of the value of the N bit and as a function of the bits of the previous character, to store into register (32), the bits which are sent on lines (6).

Abstract: An electronic postal meter has an accounting unit with redundant nonvolatile random access memories controlled by a microprocessor system. The redundant random access memories have separate groups of address and data lines to minimize identical errors in data stored therein. The data transfer may occur at different times to and from the memories, with respect to any given byte of data. The system may incorporate redundant microprocessors, and critical parameters may be checked at periodic intervals in the main program of the accounting microprocessor system.

Abstract: A sequence of instructions made up of stages is executed sequentially by the processor in a first mode (stack mode) such that, the Nth stage of the Ith instruction is processed simultaneously with the N+1 stage of the I-1 instruction. Similarly the N+1 stage of the I-1 instruction is processed at the sasme time as the N+2 stage of the I-2 instruction and so on. The processing unit maintains the execution of instructions in the same sequence as they were received by the processing unit by executing all sections of an instruction. Even though a stage may not be required for execution of a particular instruction, the processor must wait (i.e., execute a null instruction) for a time equivalent to a stage before processisng the next stage. The invention provides a second mode (non-stack mode) of execution such that unneeded or null instruction stages are bypassed without the processing order of the execution sequence being disturbed.

Abstract: An asynchronous micro-machine/interface responsive to a central processing unit (CPU) in which the CPU and the micro-machine/interface are run on clocks which are asynchronous from one another is provided. The inventive asynchronous micro-machine/interface has data path elements for receiving an incoming instruction and for performing actions requested by the incoming instruction, as well as a means for synchronizing the incoming instruction to the clock of the micro-machine/interface and for performing actions within the data path elements prior to the execution of the incoming instruction and during transfer of control, by the micro-machine/interface, to the routine that is associated with the incoming instruction.