Abstract: Provided are a data processor, and a control system, in which an interrupt controller and an event link controller are adopted. The event link controller responds to a generated event signal to output a start control signal for controlling start of an operation of a circuit module. The circuit module is able to generate an event signal. The event link controller generates the start control signal according to the correspondences between event signals and start control signals which are defined by event control information. The links between the event signals and start control signals can be prescribed by the event control information. Therefore, operations of circuit modules prescribed by such links can be controlled sequentially. The control neither involves save and return processes by CPU as in the interrupt processing, nor needs priority level control as executed on competing interrupt requests.

Abstract: This invention relates to techniques for managing a timer used in transmission or reception of data units in wireless communication. To better use the resources in a transceiver, one timer is used. Depending on how the data units being handled, the timer can be used to control a transceiver to retry transmission of data units or purge data units.

Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

Abstract: A slave-interface unit for use with a system-on-a-chip bus (such as an AXI bus) executes received transactions out-of-order while accounting for groups of in-order transactions.

Abstract: A universal serial bus (USB) communication system includes a portable instrument and a docking station that communicate with a host device using a divided USB communication device. A first portion of the USB communication device is provided in the portable instrument. A second portion of the USB communication device is provided in the docking station. The first portion includes a non-USB communication device that communicates with the second portion in a non-USB format. The second portion converts the communications into a USB format suitable for the host device.

Abstract: In one embodiment, a computer implemented method is provided for generating a network patch plan. The method can include selecting at least two devices to be interconnected. The method can include selecting a role for each of the at least two devices. The method can include identifying a patching template. The method can include determining a priority order of available logical ports associated with each of the at least two devices. The method can include generating a patch plan based on the priority order.

Abstract: An interface identification system includes an IHS enclosure including a plurality of IHS slots and a plurality of input/output (I/O) switching module slots. A connection plane provides interconnects between the plurality of IHS slots and the plurality of I/O switching module slots. An I/O switching module includes a plurality of interfaces. The I/O switching module may be coupled to a first I/O switching module slot and, in response, retrieve first I/O switching module slot information about the first I/O switching module slot, retrieve IHS information about IHSs located in the plurality of IHS slots that are interconnected with the first I/O switching module slot through the connection plane, and use the first I/O switching module slot information and the IHS information to identify each of the plurality of interfaces on the I/O switching module that is coupled to an IHS by that IHS and the first I/O switching module slot.

Abstract: A method, apparatus, and system in which an interconnect for an integrated circuit communicates transactions between one or more initiator Intellectual Property (IP) cores and one or more target IP cores coupled to the interconnect, including a power manager having a hierarchy of two or more layers including a hardware logic portion to control a power consumption of two or more domains in the integrated circuit, where each layer of the power manager performs its own function; wherein the power manager has its own dedicated CPU or dedicated state machine to execute power management instructions; and wherein the power manager controls the power consumption of two or more domains without using a CPU IP core utilized by other IP cores on the integrated circuit to execute power management instructions.

Abstract: One or more techniques and/or systems are disclosed for enabling communication between a SAS communication port of a SAS communication component and multiple storage devices. In a first example, a first SAS to SATA bridge chip and a second SAS to SATA bridge chip may be configured to route data from a SAS communication component to multiple storage devices. In a second example, a SAS to SATA bridge chip and a port multiplier may be configured to route data from a SAS communication component to multiple storage devices. In a third example, a four port SAS to SATA bridge comprising two SAS ports and two SATA ports may be configured to route data from a SAS communication component to multiple storage devices. Supporting two or more storage devices with a single SAS communication port allows storage enclosures to increase storage capacity, while decreasing cost per slot.

Abstract: A method of operating a module is disclosed. The method includes determining if a voltage between a power connection and a ground connection exceeds a predetermined threshold and if so determined then setting a module communication address to a first address, responding to a first serial communication received via the serial communication connection addressed to the module communication address, and not responding to a second serial communication received via the serial communication connection addressed to a different address than the module communication address. Other methods and devices are disclosed.

Abstract: An image forming apparatus includes a storage unit, an arbitration unit that controls access to the storage unit, and a plurality of image processing units that are connected to the arbitration unit and access the storage unit via the arbitration unit. And, an operation analysis apparatus includes: an access monitoring unit monitoring which of the image processing units the arbitration unit permits access to the storage unit; a log generation unit generating, in response to the fact that the access monitoring unit detects that the image processing unit with access permitted has been switched, information on the image processing unit with access permitted as a log; a log storage unit storing therein the generated log; and a remaining capacity determination unit determining whether the storage capacity of the log storage unit after storing the log has become equal to or smaller than a particular capacity.

Abstract: Techniques for broadcasting a command in a distributed switch, at a first switch module within the distributed switch. Embodiments receive a request to reset a PCIe link for a first host device, the first host device connected to a plurality of downstream PCIe devices through the distributed switch. A routing table specifying a plurality of downstream switch modules, connected to the first switch modules by one or more ports of the first switch module, is identified. Embodiments suspend PCIe traffic for the first host device on the one or more ports of the first switch module. Broadcast messages are transmitted to the plurality of downstream switch modules, specifying a first reset operation. Upon receiving an acknowledgement message from each of the plurality of downstream switch modules specified in the routing table, embodiments resume PCIe traffic for the first host device on the one or more ports.

Abstract: There is provided a communication system including a transmission interface, a master device and a slave device. The transmission interface includes a TR/ACK channel configured to transmit a trigger signal and an acknowledge signal and a DA channel configured to transmit a normal data or a simplified data. The master device sends the trigger signal via the TR/ACK channel before data transmission begins. The slave device sends the normal data or the simplified data to the master device via the DA channel after receiving the trigger signal.

Abstract: In a method for enabling transmission of larger data quantities relatively rapidly in a data network, the sent data frames have a logical structure according to CAN Specification ISO 11898-1, the bit length in time within a data frame being able to assume at least two different values; for a first specifiable range within the data frame, the bit length in time being greater than, or equal to a specified minimum value of approximately one microsecond and in at least one second specifiable range within the data frame the bit length in time compared to the first range is at least halved, preferably less than halved; the change of the bit length in time being implemented by using at least two different scaling factors for setting the bus time unit relative to a shortest time unit or the oscillator clock pulse during running operation.

Abstract: A method and apparatus for reconfiguring hardware structures to pipeline the execution of multiple special purpose hardware implemented functions, without saving intermediate results to memory, is provided. Pipelining functions in a program is typically performed by a first function saving its results (the “intermediate results”) to memory, and a second function subsequently accessing the memory to use the intermediate results as input. Saving and accessing intermediate results stored in memory incurs a heavy performance penalty, requires more power, consumes more memory bandwidth, and increases the memory footprint. Due to the ability to redirect the input and output of the hardware structures, intermediate results are passed directly from one special purpose hardware implemented function to another without storing the intermediate results in memory.

Abstract: A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.

Abstract: A method and system for transmitting an aggregated interrupt packet are described herein. The method includes sending metadata from a client device to a host device. The method also includes detecting at least two sets of data from the client device. Additionally, the method includes detecting an identifier for the client device. Furthermore, the method includes generating an aggregated interrupt packet in the client device that comprises the identifier and the at least two sets of data for the client device. The method also includes sending the aggregated interrupt packet from the client device to the host device.

Abstract: A control circuit (comprising, for example, a part of a charging hub for a portable electronic communications device) that is not configured to support USB On-The-Go-compatible Host Negotiation Protocol is operably coupled to a USB-ID connector and is configured to transmit an identifier via that USB-ID connector to prompt a USB device in function mode to serve as a USB host. A locally-available power supply can then serve to provide power to that USB device notwithstanding the latter's role as the host.

Abstract: A one-way bus bridge pair that transfers secure data in one direction, the bus bridge pair including a transmitting bus bridge, a receiving bus bridge, and a link. The link can connect the transmitting bus bridge and receiving bus bridge. The transmitting bus bridge may be arranged not to receive any data from the receiving bus bridge, and the receiving bus bridge may be arranged not to send any data to the transmitting bus bridge.

Abstract: Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.