Patents Examined by Brook Kebede
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Patent number: 11978835Abstract: A display device includes a substrate; a first electrode and a second electrode disposed in an emission area and a sub-region and spaced apart from each other in a first direction; a first insulating layer disposed on the first electrode and the second electrode; light emitting elements disposed on the first insulating layer in the emission area, and including ends disposed on the first and second electrodes, respectively; and a second insulating layer disposed on the first insulating layer. The second insulating layer includes a fixing pattern; a support pattern portion; and a connection portion electrically connecting the fixing pattern and the support pattern portion, and the fixing pattern includes a first region that contacts an outer surface of the light emitting elements and a second region that does not contact the outer surface of the light emitting elements.Type: GrantFiled: September 15, 2021Date of Patent: May 7, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hyun Kim, Jeong Su Park, Myeong Hun Song, Sang Hoon Lee, Jong Chan Lee
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Patent number: 11978742Abstract: A metal oxide film including a crystal part and having highly stable physical properties is provided. The size of the crystal part is less than or equal to 10 nm, which allows the observation of circumferentially arranged spots in a nanobeam electron diffraction pattern of the cross section of the metal oxide film when the measurement area is greater than or equal to 5 nm? and less than or equal to 10 nm?.Type: GrantFiled: April 20, 2023Date of Patent: May 7, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Masahiro Takahashi, Takuya Hirohashi, Masashi Tsubuku, Noritaka Ishihara, Masashi Oota
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Patent number: 11974460Abstract: A display substrate includes a plurality of sub-pixels. The display substrate further includes: a base substrate; a plurality of temperature sensors disposed on a first side of the base substrate; and a light-shielding layer disposed on a peripheral side, a side proximate to the base substrate, and a side away from the base substrate, of a temperature sensor in the temperature sensors. The temperature sensor is configured to detect a temperature of at least one of the plurality of sub-pixels. The light-shielding layer is configured to shield light emitted to the temperature sensor.Type: GrantFiled: December 28, 2020Date of Patent: April 30, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yangbing Li, Haisheng Wang, Xiaoliang Ding, Yunke Qin, Fangyuan Zhao, Wenjuan Wang, Ping Zhang
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Pixel arrangement structure, organic electroluminescent display panel, metal mask and display device
Patent number: 11974484Abstract: A pixel arrangement structure includes: first sub-pixels, second sub-pixels and third sub-pixels, being not overlapped but being spaced apart. The third sub-pixel includes a first edge facing the first sub-pixel, the first sub-pixel includes a second edge facing the third sub-pixel, the third sub-pixel includes a third edge facing the second sub-pixel, and the second sub-pixel includes a fourth edge facing the third sub-pixel, and shapes of the first sub-pixel and the second sub-pixel are circles, the first edge and the second edge are curved edges with a same curvature, the third edge and the fourth edge are curved edges with a same curvature; or shapes of the first sub-pixel and the second sub-pixel are octagons, at least part of the first edge is parallel to at least part of the second edge, at least part of the third edge is parallel to at least part of the fourth edge.Type: GrantFiled: May 31, 2023Date of Patent: April 30, 2024Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Haijun Qiu, Yangpeng Wang, Benlian Wang, Haijun Yin, Yang Wang, Yao Hu, Weinan Dai -
Patent number: 11965240Abstract: There is provided a technique that includes: removing a deposit that adheres to an interior of a process chamber by performing a cycle a predetermined number of times, the cycle including performing sequentially: (a) supplying a cleaning gas to the interior of the process chamber until an internal pressure of the process chamber rises to a first pressure range; (b) exhausting the interior of the process chamber and supplying the cleaning gas to the interior of the process chamber in parallel to maintain the internal pressure of the process chamber within the first pressure range; and (c) exhausting the interior of the process chamber until the internal pressure of the process chamber reaches a second pressure that is below the first pressure range.Type: GrantFiled: March 3, 2021Date of Patent: April 23, 2024Assignee: Kokusai Electric CorporationInventor: Keigo Nishida
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Patent number: 11967593Abstract: A semiconductor device includes a substrate; a circuit region provided with a power supply wiring, a ground wiring, and a signal line; and a first diode connected between the signal line and a first wiring. The first wiring is one of the power supply wiring and the ground wiring. The first diode includes a first impurity region of a first conductive type, electrically connected to the signal line, and a second impurity region of a second conductive type, different from the first conductive type, electrically connected to the first wiring. The signal line, the first wiring, or both is formed in the substrate.Type: GrantFiled: November 17, 2021Date of Patent: April 23, 2024Assignee: SOCIONEXT INC.Inventor: Kazuya Okubo
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Patent number: 11957922Abstract: A method is provided for producing an electrically-powered device and/or component that is embeddable in a solid structural component, and a system, a produced device and/or a produced component is provided. The produced electrically powered device includes an attached autonomous electrical power source in a form of a unique, environmentally-friendly structure configured to transform thermal energy at any temperature above absolute zero to an electric potential without any external stimulus including physical movement or deformation energy. The autonomous electrical power source component provides a mechanism for generating renewable energy as primary power for the electrically-powered device and/or component once an integrated structure including the device and/or component is deployed in an environment that restricts future access to the electrical power source for servicing, recharge, replacement, replenishment or the like.Type: GrantFiled: February 6, 2023Date of Patent: April 16, 2024Assignee: FACE INTERNATIONAL CORPORATIONInventors: Clark D Boyd, Bradbury R Face, Jeffrey D Shepard
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Patent number: 11961739Abstract: Embodiments of the present technology include semiconductor processing methods to make boron-and-silicon-containing layers that have a changing atomic ratio of boron-to-silicon. The methods may include flowing a silicon-containing precursor into a substrate processing region of a semiconductor processing chamber, and also flowing a boron-containing precursor and molecular hydrogen (H2) into the substrate processing region of the semiconductor processing chamber. The boron-containing precursor and the H2 may be flowed at a boron-to-hydrogen flow rate ratio. The flow rate of the boron-containing precursor and the H2 may be increased while the boron-to-hydrogen flow rate ratio remains constant during the flow rate increase. The boron-and-silicon-containing layer may be deposited on a substrate, and may be characterized by a continuously increasing ratio of boron-to-silicon from a first surface in contact with the substrate to a second surface of the boron-and-silicon-containing layer furthest from the substrate.Type: GrantFiled: October 5, 2020Date of Patent: April 16, 2024Assignee: Applied Materials, Inc.Inventors: Yi Yang, Krishna Nittala, Rui Cheng, Karthik Janakiraman, Diwakar Kedlaya, Zubin Huang, Aykut Aydin
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Patent number: 11955316Abstract: A substrate processing method includes: providing a substrate including a first region and a second region into a chamber; forming a deposit film on the first region and the second region of the substrate by generating a first plasma from a first processing gas, and selectively etching the first region with respect to the second region by generating a second plasma from the second processing gas containing an inert gas. The first processing gas is a mixed gas including a first gas containing carbon atoms and fluorine atoms and a second gas containing silicon atoms.Type: GrantFiled: September 29, 2020Date of Patent: April 9, 2024Assignee: TOKYO ELECTRON LIMITEDInventors: Takayuki Katsunuma, Daisuke Nishide
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Patent number: 11955543Abstract: A semiconductor device of embodiments includes: a first electrode; a second electrode; a gate electrode extending in a first direction; a silicon carbide layer between the first electrode and the second electrode and including a first silicon carbide region of a first conductive type having a first region facing the gate electrode and a second region in contact with the first electrode, a second silicon carbide region of a second conductive type, and a third silicon carbide region of a second conductive type, the first region being interposed between the second silicon carbide region and the third silicon carbide region. A first width of the first region in a second direction perpendicular to the first direction is 0.5 ?m or more than and 1.2 ?m or less. A second width of the second region in the second direction 0.5 ?m or more than and 1.5 ?m or less.Type: GrantFiled: September 9, 2021Date of Patent: April 9, 2024Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventor: Hiroshi Kono
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Patent number: 11956976Abstract: A semiconductor device including: a plurality of transistors, where at least one of the transistors includes a first single crystal source, channel, and drain, where at least one of the transistors includes a second single crystal source, channel, and drain, where the second single crystal source, channel, and drain is disposed above the first single crystal source, channel, and drain, where at least one of the transistors includes a third single crystal source, channel, and drain, where the third single crystal source, channel, and drain is disposed above the second single crystal source, channel, and drain, where at least one of the transistors includes a fourth single crystal source, channel, and drain, where the fourth single crystal source, channel, and drain is disposed above the third single crystal source, channel, and drain, and where the fourth drain is aligned to the first drain with less than 40 nm misalignment.Type: GrantFiled: August 15, 2023Date of Patent: April 9, 2024Assignee: Monolithic 3D Inc.Inventors: Deepak C. Sekar, Zvi Or-Bach
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Patent number: 11957053Abstract: A method for forming a unique, environmentally-friendly micron scale autonomous electrical power source is provided in a configuration that generates renewable energy for use in electronic systems, electronic devices and electronic system components. The configuration includes a first conductor with a facing surface conditioned to have a low work function, a second conductor with a facing surface having a comparatively higher work function, and a dielectric layer, not more than 200 nm thick, sandwiched between the respective facing surfaces of the first conductor and the second conductor. The autonomous electrical power source formed according to the disclosed method is configured to harvest minimal thermal energy from any source in an environment above absolute zero.Type: GrantFiled: July 19, 2021Date of Patent: April 9, 2024Assignee: Face International CorporationInventor: Clark D Boyd
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Patent number: 11948912Abstract: A method of manufacturing a bonded substrate stack includes: providing a first substrate having a first hybrid interface layer, the first hybrid interface layer including a first insulator and a first metal; and providing a second substrate having a second hybrid interface layer, the second hybrid interface layer including a second insulator and a second metal. The hybrid interface layers are surface-activated to generate dangling bonds on the hybrid interface layers. The surface-activated hybrid interface layers are brought into contact, such that the dangling bonds of the first hybrid interface layer and the dangling bonds of the second hybrid interface layer bond together to form first insulator to second insulator bonds and first metal to second metal bonds.Type: GrantFiled: February 1, 2023Date of Patent: April 2, 2024Assignee: Infineon Technologies AGInventors: Alfred Sigl, Alexander Frey
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Patent number: 11946136Abstract: A semiconductor processing device is disclosed. The device can include a reactor and a solid source vessel configured to supply a vaporized solid reactant to the reactor. A process control chamber can be disposed between the solid source vessel and the reactor. The device can include a valve upstream of the process control chamber. A control system can be configured to control operation of the valve based at least in part on feedback of measured pressure in the process control chamber.Type: GrantFiled: September 8, 2020Date of Patent: April 2, 2024Assignee: ASM IP Holding B.V.Inventors: Jereld Lee Winkler, Eric James Shero, Carl Louis White, Shankar Swaminathan, Bhushan Zope
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Patent number: 11942333Abstract: According to one aspect of the technique, there is provided a method of manufacturing a semiconductor device, including: (a) heating a substrate to a first temperature while supporting the substrate on a substrate support, and supplying a process gas into a process vessel accommodating the substrate support; (b) lowering a temperature of a low temperature structure provided in the process vessel to a second temperature lower than the first temperature by supplying an inert gas or air to a coolant flow path provided in the process vessel after (a) for a predetermined time, wherein defects occur when a cleaning gas is supplied to the low temperature structure at the first temperature; and (c) cleaning the low temperature structure by supplying the cleaning gas into the process vessel after (b).Type: GrantFiled: January 4, 2023Date of Patent: March 26, 2024Assignee: Kokusai Electric CorporationInventor: Tomihiro Amano
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Patent number: 11934092Abstract: A laser annealing method performed on a reflective photomask may include preparing a reflective photomask including a pattern area and a border area surrounding the pattern area and irradiating a laser beam onto the border area of the reflective photomask. The irradiating of the laser beam may include split-irradiating a plurality of laser beam spots onto the border area. Each of the plurality of laser beam spots may be shaped using a beam shaper. The beam shaper may include a blind area, a transparent area at a center of the blind area, and a semitransparent area between the blind area and the transparent area. Each of the plurality of laser beam spots may include a center portion passing through the transparent area and having a uniform energy profile and an edge portion passing through the semitransparent area and having an inclined energy profile.Type: GrantFiled: October 24, 2022Date of Patent: March 19, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hakseung Han, Sanguk Park, Jongju Park, Raewon Yi
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Patent number: 11935667Abstract: A thermionic energy conversion system, preferably including one or more electron collectors, interfacial layers, encapsulation, and/or electron emitters. A method for manufacturing the thermionic energy conversion system. A method of operation for a thermionic energy conversion system, preferably including receiving power, emitting electrons, and receiving the emitted electrons, and optionally including convectively transferring heat.Type: GrantFiled: December 20, 2021Date of Patent: March 19, 2024Assignee: Spark Thermionics, Inc.Inventors: Kyana Van Houten, Lucas Heinrich Hess, Jared William Schwede, Felix Schmitt
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Patent number: 11935986Abstract: A display device may include: a substrate including a display area and a non-display area; and pixels in the display area, and each including sub-pixels. Each sub-pixel may include a pixel circuit layer, and a display element layer including at least one light emitting element. The display element layer may include: a first electrode on the pixel circuit layer; a second electrode on the first electrode and electrically insulated from the first electrode; the light emitting element including a first end portion coupled to the first electrode and a second end portion coupled to the second electrode, and between the first electrode and the second electrode; an intermediate layer enclosing at least one area of the light emitting element, and on the first electrode; a connection line electrically connected to the second electrode. The second electrode may be on the intermediate layer.Type: GrantFiled: May 30, 2019Date of Patent: March 19, 2024Assignee: Samsung Display Co., Ltd.Inventors: Dong Uk Kim, Jin Oh Kwag, Keun Kyu Song, Sung-Chan Jo, Hyun Min Cho
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Patent number: 11935742Abstract: There is provided a technique that includes: (a) forming a film formation suppression layer on a surface of a first material of a concave portion of the substrate, by supplying a precursor to the substrate provided with the concave portion on a surface of the substrate to adsorb at least a portion of a molecular structure of molecules constituting the precursor on the surface of the first material of the concave portion, the concave portion having a top surface and a side surface composed of the first material containing a first element and a bottom surface composed of a second material containing a second element; and (b) growing a film on a surface of the second material of the concave portion by supplying a film-forming material to the substrate having the film formation suppression layer formed on the surface of the first material.Type: GrantFiled: December 14, 2022Date of Patent: March 19, 2024Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Yoshitomo Hashimoto, Kimihiko Nakatani, Takayuki Waseda
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Patent number: 11930673Abstract: A display panel includes a drive backplane, a transparent insulating layer and a light-emitting device layer. The drive backplane includes a driving circuit layer, a metal wiring layer, a first insulating layer and a reflective electrode layer. The first insulating layer has first via holes filled with first metal connectors. The reflective electrode layer includes first reflective electrodes respectively connected with the metal wiring layer through the first metal connectors. The light-emitting device layer includes a pixel electrode layer, an organic light-emitting layer and a common electrode layer. The pixel electrode layer includes first pixel electrodes respectively connected with the first reflective electrodes through the connection via holes. A distance between an orthographic projection of the connection via hole on the pixel electrode layer and an edge of the first pixel electrode is not less than a first threshold value.Type: GrantFiled: March 27, 2020Date of Patent: March 12, 2024Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhijian Zhu, Yu Ao, Yunlong Li, Pengcheng Lu, Yuanlan Tian